XRT72L52 Datasheet, PDF (91/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L52
REV. P1.1.3
the Rx FERF Condition, since the last time this regis-
ter was read.
This bit-field will be asserted under either of the fol-
lowing two conditions.
1. When the Receive DS3/E3 Framer block first
detects the occurrence of an Rx FERF Condition
(all X-bits are set to '0').
2. When the Receive DS3/E3 Framer block detects
the end of the Rx FERF Condition (all X-bits are
set to '0').
The local microprocessor can determine the current
state of the FERF Condition by reading bit 4, within
the Rx DS3 Status Register (Address = 0x11).
NOTE: For more information on the Rx FERF (Yellow
Alarm) condition, please see Section 3.3.2.5.4.
Bit 2 - (Change in) AIC Interrupt Status
This Reset Upon Read bit-field is set to "1" if the AIC
bit-field, within the incoming DS3 frames, has
changed state since the last read of this register.
NOTE: For more information on this interrupt condition,
please see Section 3.3.2.5.6.
Bit 1 - OOF Interrupt Status
This Reset Upon Read bit-field is set to "1" if the Re-
ceive DS3/E3 Framer block has detected a Change in
the Out-of-Frame (OOF) Condition, since the last time
this register was read. Therefore, this bit-field will be
asserted under either of the following two conditions:
1. When the Receive DS3/E3 Framer block has
detected the appropriate conditions to declare an
OOF Condition.
2. When the Receive DS3/E3 Framer block has
transitioned from the OOF Condition (Frame
Acquisition Mode) into the In-Frame Condition
(Frame Maintenance mode).
NOTE: For more information of the OOF Condition, please
see Section 3.3.2.2.
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