XRT72L52 Datasheet, PDF (19/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
XRT72L52
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.3
Figure 192. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and
RxNEG are to be sampled on the falling edge of RxLineClk .............................................................. 402
6.3.2 The Receive E3 Framer Block .............................................................................................................. 402
Figure 193. A Simple Illustration of the Receive E3 Framer Block and the Associated Paths to the Other
Functional Blocks ................................................................................................................................ 403
Figure 194. The State Machine Diagram for the Receive E3 Framer E3 Frame Acquisition/Maintenance Al-
gorithm ................................................................................................................................................ 404
Figure 195. Illustration of the E3, ITU-T G.832 Framing Format ........................................................ 405
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) ................................................................. 406
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11) ........................................................ 406
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) ................................................................. 407
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) ................................................................. 407
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11) ........................................................ 407
PMON FRAMING BIT/BYTE ERROR COUNT REGISTER - MSB (ADDRESS = 0X52) ................................... 408
PMON FRAMING BIT/BYTE ERROR COUNT REGISTER - LSB (ADDRESS = 0X53) .................................... 408
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11) ........................................................ 408
TABLE 86: THE RELATIONSHIP BETWEEN THE LOGIC STATE OF THE RXOOF AND RXLOF OUTPUT PINS, AND THE
FRAMING STATE OF THE RECEIVE E3 FRAMER BLOCK ............................................................................ 409
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11) ........................................................ 409
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) ................................................................. 409
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11) ........................................................ 410
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) ................................................................. 410
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11) ........................................................ 410
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11) ........................................................ 411
THE MAINTENANCE AND ADAPTATION (MA) BYTE FORMAT ....................................................................... 411
RXE3 CONFIGURATION & STATUS REGISTER 1 - (E3, ITU-T G.832) (ADDRESS = 0X10) ........................ 411
RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13) ................................................................. 412
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11) ........................................................ 412
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11) ........................................................ 412
Figure 196. Illustration of the Local Receive E3 Framer block, receiving an E3 Frame (from the Remote
Terminal) with a correct EM Byte. ....................................................................................................... 413
Figure 197. Illustration of the Local Receive E3 Framer block, transmitting an E3 Frame (to the Remote
Terminal) with the FEBE bit (within the MA byte-field) set to “0” ......................................................... 413
Figure 198. Illustration of the Local Receive E3 Framer block, receiving an E3 Frame (from the Remote
Terminal) with an incorrect EM Byte. .................................................................................................. 414
Figure 199. Illustration of the Local Receive E3 Framer block, transmitting an E3 Frame (to the Remote
Terminal) with the FEBE bit (within the MA byte-field) set to “1” ......................................................... 415
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15) ................................................................. 415
PMON PARITY ERROR COUNT REGISTER - MSB (ADDRESS = 0X54) ..................................................... 415
PMON PARITY ERROR COUNT REGISTER - LSB (ADDRESS = 0X55) ...................................................... 416
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15) ................................................................. 416
PMON FEBE EVENT COUNT REGISTER - MSB (ADDRESS = 0X56) ....................................................... 416
PMON FEBE EVENT COUNT REGISTER - LSB (ADDRESS = 0X57) ........................................................ 416
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15) ................................................................. 417
6.3.3 The Receive HDLC Controller Block ..................................................................................................... 417
Figure 200. LAPD Message Frame Format ....................................................................................... 418
RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18) ........................................................................... 419
RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18) ........................................................................... 419
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) .............................................................................. 419
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) .............................................................................. 420
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) .............................................................................. 420
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) .............................................................................. 421
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) .............................................................................. 421
TABLE 87: THE RELATIONSHIP BETWEEN THE CONTENTS OF RXLAPDTYPE[1:0] BIT-FIELDS AND THE PMDL MES-
SAGE TYPE/SIZE ................................................................................................................................... 421
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