XRT72L52 Datasheet, PDF (155/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L52
REV. P1.1.3
Figure 39 presents a simple circuit schematic that de-
picts how the XRT72L52 DS3/E3 Framer IC could be
interfaced to the XRT7300 DS3/E3/STS-1 LIU IC.
FIGURE 39. SCHEMATIC DEPICTING HOW TO INTERFACE THE XRT72L52 DS3/E3 FRAMER IC TO THE XRT73L02
DS3/E3/STS-1 LIU IC (ONE CHANNEL SHOWN)
Rx_AIS_Ch_0
RxRED_ALARM_0
Rx_OOF_Ch_0
RxLOS_Ch_0
RxFRAME_0
RxSER_CLK_0
RxDATA_IN_0
D[7:0]
A[9:0]
READY_OUT*
ALE
RD*
WR*
XRT72L52_CS*
XRT72L52_INT*
HW_RESET*
TxFRAME_0
44.736MHz
TxDATA_OUT
RxAVDD_0
DVDD_0
U1
160
159
2
3
RxAIS_0
RxRED_0
RxOOF_0
RxLOS_0
122
126
125
89
RxFrame_0
RxClk_0
RxSer_0
MOTO
RxPOS_0 ²³
RxNEG_0 ²¹
113
112
111
110
108
107
106
105
D7
D6
D5
D4
D3
D2
D1
D0
RxLineClk_0 ²⁴
RLOL_0
ExtLOS_0
152
151
103
102
101
100
99
98
97
96
95
94
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
115
92
85
91
90
116
Rdy_Dtck
ALE_AS
RDB_DS
WRB_RW
CS
INT
88 _RESET
LLOOP_0
REQB_0
TAOS_0
DMO_0
TxLEV_0
156
157
158
150
5
RLOOP_0 ¹⁵⁵
ENCODIS_0 (TxOFF_0) ⁴
TxPOS_0 ¹⁷
TxNEG_0 ¹⁶
TxLineClk_0 ¹⁸
87 _NIBBLEINTF
128
22
133
TxFrame_0
TxInClk_0
TxSer_0
XRT72L52_Ch_0
C2
0.01uF
C3
0.01uF
R7
4.7k
26 _RxAVDD0
7 _RxDVDD0
23
8
LOSTHR_0
HOST/HW
11 _RPOS0
10 _RNEG0
9 _RCLK0
U2
TxAVDD0 ³
TxAVDD0 ⁷⁴
RTIP0 ²⁸
RRING0 ²⁷
XRT71D00_CS* (Optional)
15
13
RLOL_0
RLOS_0
17
18
19
20
42
CS
SCLK
SDI
SDO
REG_RESET*
80 _{TxOFF_0}
78 _{TPDATA_0}
77 _{TNDATA_0}
79
16
TCLK_0
EXCLK_0
12 _RxDGND0
29 _RxAGND0
TTIP0 ⁷³
TRING0 ⁷²
MTIP0 ⁷⁶
MRING0 ⁷⁵
TxAGND0 ⁷¹
TxAGND0 ⁵
XRT73L02IV
C4
0.01uF
C5
0.01uF
TxAVDD
R1
R2
37.4
37.4
C1
0.01uF
6 _T2 1
4
3
T3001
R3
31.6
R4
R5
31.6
270
R6
270
1 _T1 6
3
4
T3001
J1
BNC
1
J2
BNC
1
3.1 BIT-FIELDS WITHIN THE LINE INTERFACE DRIVE
REGISTER
As mentioned above, the Line Interface Drive and
Scan section consists of five output pins and three in-
put pins. The logic state of the output pins are con-
trolled by the contents within the Line Interface Drive
register, as depicted below.
LINE INTERFACE DRIVE REGISTER (ADDRESS = 0X80)
BIT 7
ILOOP
BIT 6
BIT 5
REQB
BIT 4
TAOS
BIT 3
ENCODIS
BIT 2
TXLEV
BIT 1
RLOOP
BIT 0
LLOOP
R/O
R/O
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
1
0
0
0
The role of each of these bit-fields are their corre-
sponding output pins are depicted below.
Bit 7 - ILOOP (Internal Remote Loop-back)
This “Read/Write” bit-field permits the user to config-
ure the corresponding channel (within the XRT72L52
device) to operate in the “Internal Remote Loop-back”
Mode. Once the user configures the channel to oper-
ate in this remote loop-back mode, then the “Rx-
POSn”, “RxNEGn” and “RxLineClk_n” signals will be
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