XRT72L52 Datasheet, PDF (18/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.3
áç
PRELIMINARY
Figure 176. Flow Chart depicting how to use the LAPD Transmitter (LAPD Transmitter is configured to
transmit a LAPD Message frame only once). ...................................................................................... 384
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) ...................................................................... 385
6.2.4 The Transmit E3 Framer Block .............................................................................................................. 385
Figure 177. A Simple Illustration of the Transmit E3 Framer Block and the associated paths to other Func-
tional Blocks ........................................................................................................................................ 386
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30) ............................................................................ 387
TABLE 79: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TX AIS ENABLE) WITHIN THE TX E3 CONFIG-
URATION REGISTER, AND THE RESULTING TRANSMIT E3 FRAMER BLOCK'S ACTION .................................. 387
TABLE 80: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (TX LOS) WITHIN THE TX E3 CONFIGURATION
REGISTER, AND THE RESULTING TRANSMIT E3 FRAMER BLOCK'S ACTION ................................................ 387
6.2.5 The Transmit E3 Line Interface Block ................................................................................................... 388
Figure 178. Approach to Interfacing the XRT72L52 Framer IC device to the XRT7302 DS3/E3/STS-1 LIU
389
Figure 179. A Simple Illustration of the Transmit E3 LIU Interface block ........................................... 390
Figure 180. The Behavior of TxPOS and TxNEG signals during data transmission while the Transmit DS3
LIU Interface is operating in the Unipolar Mode .................................................................................. 390
I/O CONTROL REGISTER (ADDRESS = 0X01) .......................................................................................... 391
TABLE 81: THE RELATIONSHIP BETWEEN THE CONTENT OF BIT 3 (UNIPOLAR/BIPOLAR*) WITHIN THE UNI I/O CON-
TROL REGISTER AND THE TRANSMIT E3 FRAMER LINE INTERFACE OUTPUT MODE ................................... 391
Figure 181. Illustration of AMI Line Code ........................................................................................... 392
Figure 182. Illustration of two examples of HDB3 Encoding .............................................................. 392
I/O CONTROL REGISTER (ADDRESS = 0X01) .......................................................................................... 393
TABLE 82: THE RELATIONSHIP BETWEEN BIT 4 (AMI/HDB3*) WITHIN THE I/O CONTROL REGISTER AND THE BI-
POLAR LINE CODE THAT IS OUTPUT BY THE TRANSMIT E3 LIU INTERFACE BLOCK .................................... 393
II/O CONTROL REGISTER (ADDRESS = 0X01) ......................................................................................... 393
TABLE 83: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TXLINECLK INV) WITHIN THE I/O CONTROL
REGISTER AND THE TXLINECLK CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON ..................... 393
Figure 183. Waveform/Timing Relationship between TxLineClk, TxPOS and TxNEG - TxPOS and TxNEG
are configured to be updated on the rising edge of TxLineClk ............................................................ 394
Figure 184. Waveform/Timing Relationship between TxLineClk, TxPOS and TxNEG - TxPOS and TxNEG
are configured to be updated on the falling edge of TxLineClk ........................................................... 394
6.2.6 Transmit Section Interrupt Processing .................................................................................................. 394
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) ...................................................................... 395
TXE3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34) ...................................................... 395
TXE3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34) ...................................................... 396
6.3 THE RECEIVE SECTION OF THE XRT72L52 (E3 MODE OPERATION) .................................................................... 396
Figure 185. A Simple Illustration of the Receive Section of the XRT72L52, when it has been configured to
operate in the E3 Mode ....................................................................................................................... 396
6.3.1 The Receive E3 LIU Interface Block ...................................................................................................... 396
Figure 186. A Simple Illustration of the Receive E3 LIU Interface Block ............................................ 397
Figure 187. Behavior of the RxPOS, RxNEG and RxLineClk signals during data reception of Unipolar Data
398
II/O CONTROL REGISTER (ADDRESS = 0X01) ......................................................................................... 398
TABLE 84: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TXLINECLK INV) WITHIN THE I/O CONTROL
REGISTER AND THE TXLINECLK CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON ..................... 398
Figure 188. Illustration on how the XRT72L52 Receive E3 Framer is interfaced to the XRT7302 Line Inter-
face Unit while operating in the Bipolar mode (one channel shown) ................................................... 399
Figure 189. Illustration of AMI Line Code ........................................................................................... 400
Figure 190. Illustration of two examples of HDB3 Decoding .............................................................. 400
II/O CONTROL REGISTER (ADDRESS = 0X01) ......................................................................................... 401
TABLE 85: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (RXLINECLK INV) OF THE I/O CONTROL REG-
ISTER, AND THE SAMPLING EDGE OF THE RXLINECLK SIGNAL ................................................................... 401
Figure 191. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and
RxNEG are to be sampled on the rising edge of RxLineClk ................................................................ 402
XVI