XRT72L52 Datasheet, PDF (374/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.3
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PRELIMINARY
will also be driving the E3_Overhead_Ind input pin (of
the Terminal Equipment) "High". Whenever the Ter-
minal Equipment detects this pin toggling "High", it
should delay transmission of the very next E3 frame
payload bit by one clock cycle.
The behavior of the signals between the XRT72L52
and the Terminal Equipment for E3 Mode 2 Operation
is illustrated in Figure 160.
FIGURE 160. BEHAVIOR OF THE TERMINAL INTERFACE SIGNALS BETWEEN THE XRT72L52 AND THE TERMINAL
EQUIPMENT (MODE 2 OPERATION)
Terminal Equipment Signals
E3_Clock_In
E3_Data_Out
Tx_Start_of_Frame
E3_Overhead_Ind
Payload[4238] Payload[4239]
FA1, Bit 7
FA1, Bit 6
XRT7250 Transmit Payload Data I/F Signals
TxInClk
TxSer
Payload[4238] Payload[4239]
TxFrameRef
TxOH_Ind
FA1, Bit 7
FA1, Bit 6
E3 Frame Number N
E3 Frame Number N + 1
Note: TxOH_Ind pulses high for
16 bit periods in order to
denote Overhead Data
(e.g., the FA1 and FA2 bytes)
Note: The FA1 byte will not be processed by the
Transmit Payload Data Input Interface.
Note: TxFrameRef pulses high to denote
E3 Frame Boundary.
How to configure the XRT72L52 to operate in this
mode.
1. Set the NibIntf input pin "Low".
2. Set the TimRefSel[1:0] bit-fields (within the
Framer Operating Mode Register) to "01" as
depicted below.
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1
BIT 0
Local Loopback
DS3/E3*
Internal LOS RESET
Enable
Interrupt
Enable Reset
Frame Format
TimRefSel[1:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
1
0
1
0
0
1
3. Interface the XRT72L52, to the Terminal Equip-
ment, as illustrated in Figure 159.
6.2.1.3 Mode 3 - The Serial/Local-Timed/
Frame-Master ModeBehavior of the XRT72L52
If the XRT72L52 has been configured to operate in
this mode, then the XRT72L52 will function as fol-
lows.
A. Local Timed - Uses the TxInClk signal as the
Timing Reference
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