XRT72L52 Datasheet, PDF (261/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L52
REV. P1.1.3
4.3.6.2.8 The Detection of CP-Bit Error Inter-
rupt
If the Detection of CP-Bit Error Interrupt is enabled,
then the XRT72L52 Framer IC will generate an inter-
rupt, anytime the Receive DS3 Framer block has de-
tected a CP-bit error, within the incoming DS3 data
stream.
Enabling and Disabling the Detection of CP-Bit
Error Interrupt:
The user can enable or disable the Detection of CP-
Bit Error Interrupt, by writing the appropriate value in-
to Bit 7 (CP-Bit Error Interrupt Enable) within the
RxDS3 Interrupt Enable Register, as illustrated below.
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12)
BIT 7
CP Bit Error
Interrupt
Enable
R/W
0
BIT 6
LOS
Interrupt
Enable
R/W
0
BIT 5
AIS
Interrupt
Enable
R/W
0
BIT 4
Idle Interrupt
Enable
R/W
0
BIT 3
FERF
Interrupt
Enable
R/W
0
BIT 2
AIC
Interrupt
Enable
R/W
0
BIT 1
OOF
Interrupt
Enable
R/W
0
BIT 0
P-Bit Error
Interrupt
Enable
R/W
0
Setting this bit-field to “1” enables this interrupt. Con-
versely, setting this bit-field to “0” disables this inter-
rupt.
Servicing the Detection of CP-Bit Error Interrupt
Whenever the XRT72L52 Framer IC detects this in-
terrupt, it will do all of the following.
• It will assert the Interrupt Request output pin (INT)
by driving it "High".
• It will set Bit 7 (CP-Bit Error Interrupt Status) within
the Rx DS3 Interrupt Status Register, to “1”, as indi-
cated below.
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13)
BIT 7
CP-Bit Error
Interrupt
Status
RUR
1
BIT 6
LOS
Interrupt
Status
RUR
0
BIT 5
AIS
Interrupt
Status
RUR
0
BIT 4
Idle Interrupt
Status
RUR
0
BIT 3
FERF
Interrupt
Status
RUR
0
BIT 2
AIC
Interrupt
Status
RUR
0
BIT 1
OOF
Interrupt
Status
RUR
0
BIT 0
P-Bit Error
Interrupt
Status
RUR
1
Whenever the Terminal Equipment encounters the
Detection of CP-bit Error Interrupt, it should do the
following.
• It should read contents of PMON Frame CP-Bit
Error Count Register (located at 0x72 and 0x73), in
order to determine the number of CP-bit errors
recently received.
4.3.6.2.9 The Receive FEAC Message - Valida-
tion Interrupt
If the Receive FEAC Message - Validation Interrupt is
enabled, then the XRT72L52 Framer IC will generate
an interrupt any time the Receive FEAC Processor
validates a new FEAC (Far-End Alarm & Control)
Message.
In particular, the Receive FEAC Processor will vali-
date a FEAC Message, it that same FEAC Message
has been received in 8 of the last 10 FEAC Message
receptions.
Enabling/Disabling the Receive FEAC Message -
Validation Interrupt
The user can enable or disable the Receive FEAC
Message - Validation Interrupt, by writing the appro-
priate data into Bit 1 (RxFEAC Valid Interrupt Enable)
within the RxDS3 FEAC Interrupt Enable/Status Reg-
ister, as indicated below.
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