XRT72L52 Datasheet, PDF (48/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.3
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PRELIMINARY
AC ELECTRICAL CHARACTERISTICS (CONT.)
Test Conditions: TA = 25°C, VDD = 3.3V + 5% unless otherwise specified
SYMBOL
PARAMETER
MIN. TYP.
Microprocessor Interface - Intel (See Figure 17)
t₆₄ A(9) - A(0) Setup Time to ALE_AS Low
0
MAX.
t₆₅ A(9) - A(0) Hold Time from ALE_AS Low.
1
Intel Type Read Operations (See Figure 17 and Figure 19)
t₆₆ RD_DS, WR_R/W Pulse Width
87
t₆₇ Data Valid from RD_DS Low.
32
t₆₈ Data Bus Floating from RD_DS High
9
t₆₉ ALE to RD Time
3
t₇₀₁ RD Time to NOT READY (e.g., RDY_DTCK toggling
16
Low)
t₇₀ RD to READY Time (e.g., RDY_DTCK toggling
80
high)
t₇₆ Minimum Time between Read Burst Access (e.g.,
33
the rising edge of RD to falling edge of RD)
Intel Type Write Operations (Figure 18 and Figure 20)
t₇₁ Data Setup Time to WR_R/W High
0
t₇₂ Data Hold Time from WR_R/W High
3
t₇₃ High Time between Reads and/or Writes
33
t₇₄ ALE to WR Time
3
t₇₇ Min Time between Write Burst Access (e.g., the ris- 33
ing edge of WR to the falling edge of WR)
t₇₇₀ CS Assertion to falling edge of WR_R/W
28
Microprocessor Interface - Motorola Read Operations (See Figure 21)
t₇₈ A(9) - A(0) Setup Time to falling edge of ALE_AS
0
t₇₉ Rising edge of RD_DS to rising edge of RDY_DTCK
16
delay
t₈₀ Rising edge of RDY_DTCK to tri-state of D[7:0]
0
Microprocessor Interface - Motorola Read & Write Operations (See Figure 22)
t₇₈ A(9) - A(0) Setup Time to falling edge of ALE_AS
0
t₈₁ D[7:0] Set-up time to falling edge of RD_DS
0
t₈₂ Rising edge of RD_DS to rising edge of RDY_DTCK
13
delay
Reset Pulse Width - Both Motorola and Intel Operations (See Figure 23)
t₉₀ Reset pulse width
200
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CONDITIONS
29