XRT72L52 Datasheet, PDF (71/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L52
REV. P1.1.3
another Burst Access Operation with the XRT72L52
DS3/E3 Framer.
2.3.2.2.1.2 The Intel-Mode Write Burst Access
Whenever an Intel-type µC/µP wishes to write data in-
to a contiguous range of addresses, then it should do
the following.
a. Perform the initial write operation of the burst
access.
b. Perform the remaining write operations, of the
burst access.
c. Terminate the burst access operation.
Each of these operations within the burst access are
described below.
2.3.2.2.1.2.1 The Initial Write Operation
The initial write operation of an Intel-type Write Burst
Access is accomplished by executing a Programmed
I/O write cycle as summarized below.
A.0 Execute a Single Ordinary (Programmed I/
O) Write cycle, as described in Steps A.1
through A.7 below.
A.1 Place the address of the initial target register
(or buffer location) within the Framer, on the
Address Bus pins, A[10:0].
A.2 At the same time, the Address-Decoding cir-
cuitry (within the user's system) should assert
the CS (Chip Select) input pin of the Framer, by
toggling it "Low". This step enables further
communication between the µC/µP and the
Framer Microprocessor Interface block.
A.3 Assert the ALE_AS (Address Latch Enable)
input pin "High". This step enables the Address
Bus input drivers, within the Microprocessor
Interface Block of the Framer.
A.4 After allowing the data on the Address Bus pins
to settle (by waiting the appropriate Address
Setup time), the µC/µP should then toggle the
ALE_AS input pin "Low". This step latches the
contents, on the Address Bus pins, A[10:0], into
the XRT72L52 DS3/E3 Framer Microprocessor
Interface block. At this point, the initial address
of the burst access has now been selected.
NOTE: The ALE_AS input pin should remain "Low" for the
remainder of this Burst I/O Access operation.
A.5 Next, the µC/µP should indicate that this cur-
rent bus cycle is a Write operation by keeping
the RD_DS pin "High" and toggling the WR_R/
W (Write Strobe) pin "Low". This action also
enables the bi-directional data bus input drivers
of the Framer device.
A.6 The µC/µP places the byte (or word) that it
intends to write into the target register on the
bi-directional data bus, D[7:0].
A.7 After waiting the appropriate amount of time, for
the data (on the bi-directional data bus) to set-
tle, the µC/µP should toggle the WR_R/W (Write
Strobe) input pin "High". This action accom-
plishes two things.
a. It latches the contents of the bi-directional data
bus into the XRT72L52 DS3/E3 Framer Micropro-
cessor Interface Block.
b. It terminates the write cycle.
Figure 31 presents a timing diagram which illustrates
the behavior of the Microprocessor Interface signals,
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