XRT72L52 Datasheet, PDF (60/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52 TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.3
áç
PRELIMINARY
2.0 THE MICROPROCESSOR INTERFACE
BLOCK
The Microprocessor Interface section supports com-
munication between the local microprocessor (µP)
and the Framer IC. In particular, the Microprocessor
Interface section supports the following operations
between the local microprocessor and the Framer.
• Channel Selection
• The writing of configuration data into the Framer
on-chip (addressable) registers.
• The writing of an outbound PMDL (Path Mainte-
nance Data Link) message into the Transmit LAPD
Message buffer (within the Framer IC).
• The Framer IC's generation of an Interrupt Request
to the µP.
• The µP's servicing of the interrupt request from the
Framer IC.
• The monitoring of the system's health by periodi-
cally reading the on-chip Performance Monitor reg-
isters.
• The reading of an inbound PMDL Message from
the Receive LAPD Message Buffer (within the
Framer IC).
Each of these operations (between the local micro-
processor and the Framer IC) will be discussed in
some detail, throughout this data sheet.
2.1 CHANNEL SELECTION WITHIN THE XRT72L52
DEVICE
The XRT72L52 2-Channel DS3/E3 Clear Channel
Framer IC consists of two independent banks of
"Configuration" registers. Each of these banks are
identical and correspond to each of the two channels
within the XRT72L52. The XRT72L52 permits the us-
er to select and access any one of these Configura-
tion Register Banks, via the Most Significant Address
Pin A(9).
The relationship between the states of A(9) and the
corresponding "Configuration Register" bank, is tabu-
lated below.
TABLE 1: THE RELATIONSHIP BETWEEN ADDRESS BITS
A(9) AND THE SELECTED CONFIGURATION REGISTER
BANK
A(9)
CONFIGURATION REGISTER BANK SELECTED
0
Channel 0
1
Channel 1
The remaining Address Bus pins [A(8) through A(0)
are used to select the individual configuration regis-
ters (within the selected configuration register bank)
for Read/Write access.
Looking at this Another Way
Each of the two (2) Configuration Register Banks,
within the XRT72L52 DS3/E3 Framer IC has an iden-
tical set of configuration registers. However, address
pin A(9) imposes the following address location off-
set, for each of the Configuration Register Bank with-
in the address space of the XRT72L52 device.
CONFIGURATION REGISTER ADDRESS OFFSET (WITHIN THE
BANK - CHANNEL NUMBER XRT72L52 ADDRESS SPACE)
0
0x000
1
0x200
Figure 24 presents a simple block diagram of the Mi-
croprocessor Interface Section, within the Framer IC.
41