XRT72L52 Datasheet, PDF (144/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52 TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.3
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PRELIMINARY
• XRT7302 2-Channel DS3/E3/STS-1 LIU IC (5V)
• XRT73L03 3-Channel DS3/E3/STS-1 LIU IC (3.3V)
• XRT73L04 4-Channel DS3/E3/STS-1 LIU IC (3.3V)
NOTE: Asserting the RLOS input pin will cause the
XRT72L52 Framer IC device to generate the Change in
LOS Condition interrupt and declare an LOS (Loss of Sig-
nal) condition. Therefore, this input pin should not be used
as a general purpose input.
2.4.8.21 HDLC Control Register
HDLC CONTROL REGISTER (ADDRESS = 0X82)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Framer
By-Pass
HDLC
ON
CRC-32
Select
Reserved
HDLC
Loop-Back
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit 7 - Framer By-Pass
This “Read/Write” bit-field permits the user to enable
or disable (by-pass) the DS3/E3 Framer circuitry,
within a given channel in the XRT72L52 device.
This feature permits the user to operate a given
Channel in the “Un-framed” Mode. Further, this fea-
ture also permits the user to transmit and receive
HDLC frames at the DS3 or E3 line rate of
44.736Mbps or 34.368Mbps, without sacrificing any
bandwidth to support the overhead bits/bytes/
Setting this bit-field to “1” disables the “Transmit and
Receive DS3/E3 Framer” blocks within the channel.
Setting this bit-field to “0” enables the “Transmit and
Receive DS3/E3 Framer” blocks.
Bit 6 - HDLC ON
This “Read/Write” bit-field permits the user to config-
ure a given channel to operate in the “High-Speed
HDLC Controller” Mode. If the user invokes this fea-
ture, then a Transmit and Receive byte-wide interface
will be enabled, and the channel will be configured to
transmit and receive HDLC Frames via the DS3 or E3
payload bits.
Setting this bit-field to “1” configures the channel to
operate in the “High-Speed HDLC Controller” Mode.
Bit 5 - CRC-32
This “Read/Write” bit-field permits the user to config-
ure a given channel to do the following.
1. To configure the Transmit HDLC Controller block
to compute and append either a CRC-16 or a
CRC-32 value as a trailer to the “outbound”
HDLC frame.
2. To configure the Receive HDLC Controller block
to compute and verify either CRC-16 or the CRC-
32 value within each “inbound” HDLC frame.
Setting this bit-field to “0” configures the Transmit
HDLC Controller block to compute and append the
CRC-16 value to the end of the “outbound” HDLC
frame. Further, this setting also configures the Re-
ceive HDLC Controller block compute and verify the
CRC-32 value, which has been appended to the end
of the “inbound” HDLC frame.
Setting this bit-field to “1” configures the Transmit
HDLC Controller block to compute and append the
CRC-32 value to the end of the “outbound” HDLC
frame. Further, this same setting also configures the
Receive HDLC Controller block to compute and verify
the CRC-32 value, which has been appended to the
end of the “inbound” HDLC frame.
NOTE: This bit-field is only active if the channel has been
configured to operate in the “High-Speed HDLC Controller”
Mode.
Bit 3 - HDLC Loop-Back
2.5 THE LOSS OF CLOCK ENABLE FEATURE
The timing for the Microprocessor Interface section,
originates from a line rate (e.g., either a 34.368MHz
or 44.736 MHz) signal that is provided by either the
TxInClk[n] or the RxLineClk[n] signals. However, if
the Framer device experiences a Loss of Clock signal
event such that neither the TxInClk[n] nor the RxLi-
neClk[n] signal are present, then the Framer Micro-
processor Interface section cease to function.
The Framer device offers a Loss of Clock (LOC) pro-
tection feature that allows the Microprocessor Inter-
face section to at least complete or terminate an in-
process Read or Write cycle (with the local µP)
should this Loss of Clock event occur. The LOC cir-
cuitry consists of a ring oscillator that continuously
checks for signal transitions at the TxInClk[n] and Rx-
LineClk[n] input pins. If a Loss of Clock Signal event
occur such that no transitions are occurring on these
pins, then the LOC circuitry will automatically assert
the RDY_DTCK signal in order to complete (or termi-
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