XRT72L52 Datasheet, PDF (10/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.3
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PRELIMINARY
196
II/O CONTROL REGISTER (ADDRESS = 0X01) ......................................................................................... 197
TABLE 36: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TXLINECLK INV) WITHIN THE I/O CONTROL
REGISTER AND THE TXLINECLK CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON ..................... 197
Figure 75. Illustration on how the Receive DS3 Framer (within the XRT72L52 Framer IC) being interfaced
to theXRT7302 LIU, while the Framer is operating in Bipolar Mode (one channel shown) ................. 197
Figure 76. Illustration of AMI Line Code ............................................................................................. 198
Figure 77. Illustration of two examples of B3ZS Decoding ................................................................. 199
II/O CONTROL REGISTER (ADDRESS = 0X01) ......................................................................................... 199
TABLE 37: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (RXLINECLK INV) OF THE I/O CONTROL REG-
ISTER, AND THE SAMPLING EDGE OF THE RXLINECLK SIGNAL ................................................................... 199
Figure 78. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and
RxNEG are to be sampled on the rising edge of RxLineClk ................................................................ 200
Figure 79. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and
RxNEG are to be sampled on the falling edge of RxLineClk ............................................................... 200
4.3.2 The Receive DS3 Framer Block ............................................................................................................ 200
Figure 80. A Simple Illustration of the Receive DS3 Framer Block and the Associated Paths to the Other
Functional Blocks ................................................................................................................................ 201
Figure 81. The State Machine Diagram for the Receive DS3 Framer block's Frame Acquisition/Mainte-
nance Algorithm ................................................................................................................................... 202
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ................................................... 203
TABLE 38: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (FRAMING ON PARITY) WITHIN THE RX DS3
CONFIGURATION AND STATUS REGISTER, AND THE RESULTING FRAMING ACQUISITION CRITERIA .............. 203
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ................................................... 203
TABLE 39: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (F-SYNC ALGO) WITHIN THE RX DS3 CONFIG-
URATION AND STATUS REGISTER, AND THE RESULTING F-BIT OOF DECLARATION CRITERIA USED BY THE RECEIVE
DS3 FRAMER BLOCK ............................................................................................................................. 204
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ................................................... 204
TABLE 40: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 0 (M-SYNC ALGO) WITHIN THE RX DS3 CONFIG-
URATION AND STATUS REGISTER, AND THE RESULTING M-BIT OOF DECLARATION CRITERIA USED BY THE RE-
CEIVE DS3 FRAMER BLOCK .................................................................................................................... 204
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ................................................... 204
I/O CONTROL REGISTER (ADDRESS = 0X01) .......................................................................................... 205
PMON FRAMING BIT ERROR EVENT COUNT REGISTER - MSB (ADDRESS = 0X52) ................................. 205
PMON FRAMING BIT ERROR EVENT COUNT REGISTER - LSB (ADDRESS = 0X53) .................................. 205
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ................................................... 206
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ................................................... 206
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ................................................... 207
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ................................................... 207
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ................................................... 207
RX DS3 STATUS REGISTER (ADDRESS = 0X11) ..................................................................................... 208
RX DS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) .................................................................... 208
RXDS3 STATUS REGISTER (ADDRESS = 0X11) ...................................................................................... 209
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) ..................................................................... 209
PMON PARITY ERROR EVENT COUNT REGISTER - MSB (ADDRESS = 0X54) .......................................... 209
PMON PARITY ERROR EVENT COUNT REGISTER - LSB (ADDRESS = 0X55) ........................................... 209
Figure 82. A Simple Illustration of the Locations of the Source, Mid-Network and Sink Terminal Equipment
(for CP-Bit Processing) ........................................................................................................................ 210
Figure 83. Illustration of the Presumed Configuration of the Mid-Network Terminal Equipment ........ 211
4.3.3 The Receive HDLC Controller Block ..................................................................................................... 212
RX DS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17) ............................................ 213
RX DS3 FEAC REGISTER (ADDRESS = 0X16) ....................................................................................... 213
RX DS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17) ............................................ 213
Figure 84. Flow Diagram depicting how the Receive FEAC Processor Functions ............................. 214
Figure 85. LAPD Message Frame Format .......................................................................................... 215
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