XRT72L52 Datasheet, PDF (6/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.3
áç
PRELIMINARY
TXE3 TTB-5 REGISTER (ADDRESS = 0X3D) .......................................................................................... 107
TXE3 TTB-6 REGISTER (ADDRESS = 0X3E) ........................................................................................... 107
TXE3 TTB-7 REGISTER (ADDRESS = 0X3F) ........................................................................................... 107
TXE3 TTB-8 REGISTER (ADDRESS = 0X40) ........................................................................................... 108
TXE3 TTB-9 REGISTER (ADDRESS = 0X41) ........................................................................................... 108
TXE3 TTB-10 REGISTER (ADDRESS = 0X42) ......................................................................................... 109
TXE3 TTB-11 REGISTER (ADDRESS = 0X43) ......................................................................................... 109
TXE3 TTB-12 REGISTER (ADDRESS = 0X44) ......................................................................................... 109
TXE3 TTB-13 REGISTER (ADDRESS = 0X45) ......................................................................................... 110
TXE3 TTB-14 REGISTER (ADDRESS = 0X46) ......................................................................................... 110
TXE3 TTB-15 REGISTER (ADDRESS = 0X47) ......................................................................................... 110
TXE3 FA1 ERROR MASK REGISTER (ADDRESS = 0X48) ......................................................................... 111
TXE3 FA2 ERROR MASK REGISTER (ADDRESS = 0X49) ......................................................................... 111
TXE3 BIP-8 ERROR MASK REGISTER (ADDRESS = 0X4A) ...................................................................... 111
2.4.7 Transmit E3 Framer Configuration Registers (ITU-T G.751) ................................................................. 112
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30) ............................................................................ 112
TXE3 LAPD CONFIGURATION REGISTER (ADDRESS = 0X33) .................................................................. 113
TXE3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34) ...................................................... 114
TXE3 SERVICE BITS REGISTER (ADDRESS = 0X35) ................................................................................ 115
TXE3 FAS ERROR MASK REGISTER - 0 (ADDRESS = 0X48) ................................................................... 115
TXE3 FAS ERROR MASK REGISTER - 1 (ADDRESS = 0X49) ................................................................... 115
TXE3 BIP-4 ERROR MASK REGISTER (ADDRESS = 0X4A) ...................................................................... 116
2.4.8 Performance Monitor Registers ............................................................................................................. 116
PMON LCV EVENT COUNT REGISTER - LSB (ADDRESS = 0X51) ........................................................... 116
PMON FRAMING BIT/BYTE ERROR COUNT REGISTER - MSB (ADDRESS = 0X52) ................................... 117
PMON FRAMING BIT/BYTE ERROR COUNT REGISTER - LSB (ADDRESS = 0X53) .................................... 117
PMON PARITY ERROR COUNT REGISTER - MSB (ADDRESS = 0X54) ..................................................... 117
PMON PARITY ERROR COUNT REGISTER - LSB (ADDRESS = 0X55) ...................................................... 117
PMON FEBE EVENT COUNT REGISTER - MSB (ADDRESS = 0X56) ........................................................ 118
PMON FEBE EVENT COUNT REGISTER - LSB (ADDRESS = 0X57) ......................................................... 118
PMON CP-BIT ERROR COUNT REGISTER - MSB (ADDRESS = 0X58) ..................................................... 118
PMON CP-BIT ERROR COUNT REGISTER - LSB (ADDRESS = 0X59) ...................................................... 119
PMON HOLDING REGISTER (ADDRESS = 0X6C) ..................................................................................... 119
ONE-SECOND ERROR STATUS REGISTER (ADDRESS = 0X6D) ................................................................ 119
LCV - ONE-SECOND ACCUMULATOR REGISTER - MSB (ADDRESS = 0X6E) ............................................ 120
LCV - ONE-SECOND ACCUMULATOR REGISTER - LSB (ADDRESS = 0X6F) .............................................. 120
FRAME PARITY ERRORS - ONE-SECOND ACCUMULATOR REGISTER - MSB (ADDRESS = 0X70) ................ 120
FRAME PARITY ERRORS - ONE-SECOND ACCUMULATOR REGISTER - LSB (ADDRESS = 0X71) ................. 121
FRAME CP-BIT ERRORS - ONE-SECOND ACCUMULATOR REGISTER - MSB (ADDRESS = 0X72) ............... 121
FRAME PARITY ERRORS - ONE-SECOND ACCUMULATOR REGISTER - LSB (ADDRESS = 0X73) ................. 121
LINE INTERFACE DRIVE REGISTER (ADDRESS = 0X80) ............................................................................ 122
LINE INTERFACE SCAN REGISTER (ADDRESS = 0X81) ............................................................................. 124
HDLC CONTROL REGISTER (ADDRESS = 0X82) ..................................................................................... 125
2.5 THE LOSS OF CLOCK ENABLE FEATURE ............................................................................................................. 125
ADDRESS = 0X01, FRAMER I/O CONTROL REGISTER .............................................................................. 126
2.6 USING THE PMON HOLDING REGISTER .............................................................................................................. 126
2.7 THE INTERRUPT STRUCTURE WITHIN THE FRAMER MICROPROCESSOR INTERFACE SECTION ................................. 126
TABLE 6: LIST OF ALL OF THE POSSIBLE CONDITIONS THAT CAN GENERATE INTERRUPTS WITHIN EACH CHANNEL
OF THE XRT72L52 FRAMER DEVICE ...................................................................................................... 127
TABLE 7: A LISTING OF THE XRT72L52 FRAMER DEVICE INTERRUPT BLOCK REGISTERS (FOR DS3 APPLICA-
TIONS) ................................................................................................................................................... 127
TABLE 8: A LISTING OF THE XRT72L52 FRAMER DEVICE INTERRUPT BLOCK REGISTERS (FOR E3, ITU-T G.832
APPLICATIONS) ...................................................................................................................................... 127
TABLE 9: A LISTING OF THE XRT72L52 FRAMER DEVICE INTERRUPT BLOCK REGISTER (FOR E3, ITU-T G.751
APPLICATIONS) ...................................................................................................................................... 128
IV