XRT72L52 Datasheet, PDF (13/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
XRT72L52
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.3
Figure 112. Simple Illustration of the Transmit Overhead Data Input Interface block ........................ 265
TABLE 48: A LISTING OF THE OVERHEAD BITS WITHIN THE E3 FRAME, AND THEIR POTENTIAL SOURCES, WITHIN
THE XRT72L52 IC ................................................................................................................................ 266
TABLE 49: DESCRIPTION OF METHOD 1 TRANSMIT OVERHEAD INPUT INTERFACE SIGNALS ..................... 267
Figure 113. Illustration of the Terminal Equipment being interfaced to the Transmit Overhead Data Input
Interface (Method 1) ............................................................................................................................ 268
TABLE 50: THE RELATIONSHIP BETWEEN THE NUMBER OF RISING CLOCK EDGES IN TXOHCLK, (SINCE TXO-
HFRAME WAS LAST SAMPLED "HIGH") TO THE E3 OVERHEAD BIT, THAT IS BEING PROCESSED ................. 269
Figure 114. Illustration of the signal that must occur between the Terminal Equipment and the XRT72L52
in order to configure the XRT72L52 to transmit a Yellow Alarm to the remote terminal equipment ... 270
TABLE 51: DESCRIPTION OF METHOD 2 TRANSMIT OVERHEAD INPUT INTERFACE SIGNALS ..................... 271
Figure 115. Illustration of the Terminal Equipment being interfaced to the Transmit Overhead Data Input
Interface (Method 2) ............................................................................................................................ 272
TABLE 52: THE RELATIONSHIP BETWEEN THE NUMBER OF TXOHENABLE PULSES (SINCE THE LAST OCCURRENCE
OF THE TXOHFRAME PULSE) TO THE E3 OVERHEAD BIT, THAT IS BEING PROCESSED BY THE XRT72L52 273
Figure 116. Behavior of Transmit Overhead Data Input Interface signals between the XRT72L52 and the
Terminal Equipment (for Method 2) .................................................................................................... 274
5.2.3 The Transmit E3 HDLC Controller ........................................................................................................ 274
Figure 117. LAPD Message Frame Format ....................................................................................... 275
TABLE 53: THE LAPD MESSAGE TYPE AND THE CORRESPONDING VALUE OF THE FIRST BYTE, WITHIN THE INFOR-
MATION PAYLOAD .................................................................................................................................. 275
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30) ............................................................................ 276
TRANSMIT E3 LAPD CONFIGURATION REGISTER (ADDRESS = 0X33) ..................................................... 276
TABLE 54: RELATIONSHIP BETWEEN TXLAPD MSG LENGTH AND THE LAPD MESSAGE SIZE .................. 277
TXE3 LAPD CONFIGURATION REGISTER (ADDRESS = 0X33) ................................................................. 277
TRANSMIT E3 LAPD CONFIGURATION REGISTER (ADDRESS = 0X33) ..................................................... 277
TXE3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34) ...................................................... 278
TXE3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34) ...................................................... 278
Figure 118. Flow Chart Depicting how to use the LAPD Transmitter ................................................. 280
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) ..................................................................... 281
5.2.4 The Transmit E3 Framer Block ............................................................................................................. 282
Figure 119. A Simple Illustration of the Transmit E3 Framer Block and the associated paths to other Func-
tional Blocks ........................................................................................................................................ 283
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30) ............................................................................ 283
TABLE 55: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TX AIS ENABLE) WITHIN THE TX E3 CONFIG-
URATION REGISTER, AND THE RESULTING TRANSMIT E3 FRAMER BLOCK'S ACTION ................................. 284
TABLE 56: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (TX LOS) WITHIN THE TX E3 CONFIGURATION
REGISTER, AND THE RESULTING TRANSMIT E3 FRAMER BLOCK'S ACTION ............................................... 284
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30) ............................................................................ 284
TXE3 SERVICE BITS REGISTER (ADDRESS = 0X35) ................................................................................ 285
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30) ............................................................................ 285
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30) ............................................................................ 286
TXE3 FAS ERROR MASK REGISTER - 0 (ADDRESS = 0X48) ................................................................... 286
TXE3 FAS ERROR MASK REGISTER - 1 (ADDRESS = 0X49) ................................................................... 286
TXE3 BIP-4 ERROR MASK REGISTER (ADDRESS = 0X4A) ...................................................................... 287
5.2.5 The Transmit E3 Line Interface Block ................................................................................................... 287
Figure 120. Approach to Interfacing the XRT72L52 Framer IC to the XRT7302 DS3/E3/STS-1 LIU 288
Figure 121. A Simple Illustration of the Transmit E3 LIU Interface block ........................................... 289
Figure 122. The Behavior of TxPOS and TxNEG signals during data transmission while the Transmit DS3
LIU Interface is operating in the Unipolar Mode .................................................................................. 289
I/O CONTROL REGISTER (ADDRESS = 0X01) .......................................................................................... 290
TABLE 57: THE RELATIONSHIP BETWEEN THE CONTENT OF BIT 3 (UNIPOLAR/BIPOLAR*) WITHIN THE UNI I/O CON-
TROL REGISTER AND THE TRANSMIT E3 FRAMER LINE INTERFACE OUTPUT MODE .................................. 290
Figure 123. Illustration of AMI Line Code ........................................................................................... 291
Figure 124. Illustration of two examples of HDB3 Encoding .............................................................. 291
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