XRT72L52 Datasheet, PDF (206/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52 TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.3
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PRELIMINARY
The XRT72L52 Framer IC is a digital device that
takes DS3 payload and overhead bit information from
some terminal equipment, processes this data and ul-
timately, multiplexes this information into a series of
outbound DS3 frames. However, for DS3 coaxial ca-
ble applications, the XRT72L52 Framer IC lacks the
current drive capability to be able to directly transmit
this DS3 data stream through some transformer-cou-
pled coax cable with enough signal strength for it to
comply with the Isolated Pulse Template require-
ments and be received by the remote receiver.
Therefore, in order to get around this problem, the
Framer IC requires the use of an LIU (Line Interface
Unit) IC. An LIU is a device that has sufficient drive
capability, along with the necessary pulse-shaping
circuitry to be able to transmit a signal through the
transmission medium in a manner that it can (1) com-
ply with the DSX-3 Isolated Pulse Template require-
ments and (2) be reliably received by the Remote Ter-
minal Equipment. Figure 65 presents a circuit draw-
ing depicting the Framer IC interfacing to an LIU
(XRT7300 DS3/E3/STS-1 Transmit LIU).
FIGURE 65. APPROACH TO INTERFACING THE XRT72L52 FRAMER IC TO THE XRT7302 DS3/E3/STS-1 TRANSMIT-
TER LIU (ONE CHANNEL SHOWN)
Rx_AIS_Ch_0
RxRED_ALARM_0
Rx_OOF_Ch_0
RxLOS_Ch_0
RxFRAME_0
RxSER_CLK_0
RxDATA_IN_0
D[7:0]
A[9:0]
READY_OUT*
ALE
RD*
WR*
XRT72L52_CS*
XRT72L52_INT*
HW_RESET*
TxFRAME_0
44.736MHz
TxDATA_OUT
RxAVDD_0
DVDD_0
U1
160
159
2
3
RxAIS_0
RxRED_0
RxOOF_0
RxLOS_0
122
126
125
89
RxFrame_0
RxClk_0
RxSer_0
MOTO
RxPOS_0 ²³
RxNEG_0 ²¹
113
112
111
110
108
D7
D6
D5
D4
107
106
105
D3
D2
D1
D0
RxLineClk_0 ²⁴
RLOL_0
ExtLOS_0
152
151
103
102
101
100
99
A9
A8
A7
A6
98
97
96
95
94
A5
A4
A3
A2
A1
A0
115
92
85
91
90
Rdy_Dtck
ALE_AS
RDB_DS
WRB_RW
116
CS
INT
88 _RESET
LLOOP_0
REQB_0
TAOS_0
DMO_0
156
157
158
150
5
TxLEV_0
RLOOP_0 ¹⁵⁵
ENCODIS_0 (TxOFF_0)
4
TxPOS_0 ¹⁷
16
TxNEG_0
TxLineClk_0 ¹⁸
87 _NIBBLEINTF
128
22
133
TxFrame_0
TxInClk_0
TxSer_0
XRT72L52_Ch_0
C2
0.01uF
C3
0.01uF
R7
4.7k
26 _RxAVDD0
7
RxDVDD0
23
8
LOSTHR_0
HOST/HW
11 _RPOS0
10 _RNEG0
9 _RCLK0
U2
TxAVDD0 ³
74
TxAVDD0
RTIP0 ²⁸
RRING0 ²⁷
XRT71D00_CS* (Optional)
15
13
RLOL_0
RLOS_0
17
18
19
20
42
CS
SCLK
SDI
SDO
REG_RESET*
80 _{TxOFF_0}
78 _{TPDATA_0}
77
TNDATA_0
79
16
TCLK_0
EXCLK_0
12 _RxDGND0
29 _RxAGND0
TTIP0 ⁷³
TRING0 ⁷²
MTIP0 ⁷⁶
MRING0 ⁷⁵
TxAGND0 ⁷¹
TxAGND0 ⁵
XRT73L02IV
C4
0.01uF
C5
0.01uF
TxAVDD
R1
R2
37.4
37.4
C1
0.01uF
6 _T2 1
4
3
T3001
R3
31.6
R4
R5
31.6
270
R6
270
1 _T1 6
3
4
T3001
J1
BNC
1
J2
BNC
1
The Transmit Section of the XRT72L52 contains a
block which is known as the Transmit DS3 LIU Inter-
face block. The purpose of the Transmit DS3 LIU In-
terface block is to take the outbound DS3 data
stream, from the Transmit DS3 Framer block, and to
do the following:
1. Encode this data into one of the following line
codes
a. Unipolar (e.g., Single-Rail)
b. AMI (Alternate Mark Inversion)
c. B3ZS (Bipolar 3 Zero Substitution)
2. And to transmit this data to the LIU IC.
Figure 66 presents a simple illustration of the Trans-
mit DS3 LIU Interface block.
187