XRT72L52 Datasheet, PDF (466/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.3
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PRELIMINARY
Status), within the Rx E3 Interrupt Status Register -
2 to “1”, as indicated below
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15)
BIT 7
Not Used
RO
0
BIT 6
TTB
Change
Interrupt
Status
RUR
0
BIT 5
Not Used
RO
0
BIT 4
FEBE
Interrupt
Status
RUR
0
BIT 3
FERF
Interrupt
Status
RUR
1
BIT 2
BIP-8
Error Interrupt
Status
RUR
0
BIT 1
Framing
Byte Error
Interrupt
Status
RUR
0
BIT 0
RxPld
Mis
Interrupt
Status
RUR
0
Whenever the user’s system encounters the Change
in Receive FERF Condition Interrupt, then it should
do the following.
1. It should determine the current state of the FERF
condition. Recall, that this interrupt can be gen-
erated, whenever the XRT72L52 Framer IC
declares or clears the FERF defect. Hence, the
user can determine the current state of the LOS
defect by reading the state of Bit 0 (RxFERF)
within the Rx E3 Configuration and Status Regis-
ter - 2, as illustrated below.
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11)
BIT 7
Rx LOF Algo
R/W
X
BIT 6
RxLOF
RO
X
BIT 5
RxOOF
RO
X
BIT 4
RxLOS
RO
X
BIT 3
RxAIS
RO
X
BIT 2
RxPld Unstab
RO
X
BIT 1
Rx
TMark
RO
X
BIT 0
RxFERF
RO
X
6.3.6.2.8 The Detection of FEBE (Far-End-
Block Error) Event Interrupt
If the Detection of FEBE Event Interrupt is enabled,
then the XRT72L52 Framer IC will generate an inter-
rupt, anytime the Receive E3 Framer block has re-
ceived an E3 frame with the FEBE bit-field (within the
MA byte) set to “1”.
Enabling and Disabling the Detection of FEBE
Event Interrupt
The user can enable or disable the Detection of
FEBE Event’ interrupt by writing the appropriate value
into Bit 4 (FEBE Interrupt Enable) within the Rx E3 In-
terrupt Enable Register - 2, as indicated below.
RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13)
BIT 7
Not Used
RO
0
BIT 6
TTB
Change
Interrupt
Enable
R/W
0
BIT 5
Not Used
RO
0
BIT 4
FEBE
Interrupt
Enable
R/W
X
BIT 3
FERF
Interrupt
Enable
R/W
X
BIT 2
BIP-8
Error Interrupt
Enable
R/W
0
BIT 1
Framing
Byte Error
Interrupt
Enable
R/W
0
BIT 0
RxPld
Mis
Interrupt
Enable
R/W
0
Setting this bit-field to “1” enables this interrupt. Con-
versely, setting this bit-field to “0” disables this inter-
rupt.
Servicing the Detection of the FEBE Event Inter-
rupt
Whenever the XRT72L52 Framer IC detects this in-
terrupt, it will do the following.
• It will assert the Interrupt Request output pin (INT),
by driving it “High”.It will set the Bit 4 (FEBE Inter-
rupt Status), within the RxE3 Interrupt Status Reg-
ister - 2 as indicated below.
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