XRT72L52 Datasheet, PDF (342/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.3
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PRELIMINARY
TABLE 64: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT
INTERFACE BLOCK (FOR METHOD 1)
SIGNAL NAME
RxOH
RxOHClk
RxOHFrame
TYPE
DESCRIPTION
Output
Receive Overhead Data Output pin:
The XRT72L52 will output the overhead bits, within the incoming E3 frames, via this pin.
The Receive Overhead Data Output Interface block will output a given overhead bit, upon the
falling edge of RxOHClk. Hence, the external data link equipment should sample the data, at
this pin, upon the rising edge of RxOHClk.
NOTE: The XRT72L52 will always output the E3 Overhead bits via this output pin. There are no
external input pins or register bit settings available that will disable this output pin.
Output
Receive Overhead Data Output Interface Clock Signal:
The XRT72L52 will output the Overhead bits (within the incoming E3 frames), via the RxOH
output pin, upon the falling edge of this clock signal.
As a consequence, the user's data link equipment should use the rising edge of this clock sig-
nal to sample the data on both the RxOH and RxOHFrame output pins.
NOTE: This clock signal is always active.
Output ^{Receive Overhead Data Output Interface - Start of Frame Indicator:}
The XRT72L52 will drive this output pin "High” (for one period of the RxOHClk signal) whenever
the first overhead bit within a given E3 frame is being driven onto the RxOH output pin.
Table 65 relates the number of rising clock edges (in
the RxOHClk signal, since the RxOHFrame signal
was last sampled "High”) to the E3 Overhead bit that
is being output via the RxOH output pin.
TABLE 65: THE RELATIONSHIP BETWEEN THE NUMBER OF RISING CLOCK EDGES IN RXOHCLK, (SINCE
RXOHFRAME WAS LAST SAMPLED "HIGH”) TO THE E3 OVERHEAD BIT, THAT IS BEING OUTPUT VIA THE RXOH
OUTPUT PIN
NUMBER OF RISING CLOCK EDGES IN RXOHCLK
0 (Clock edge is coincident with RxOHFrame being detected "High”)
1
2
3
4
5
6
7
8
9
10
11
THE OVERHEAD BIT BEING OUTPUT BY THE
XRT72L52
FAS Pattern - Bit 9
FAS Pattern - Bit 8
FAS Pattern - Bit 7
FAS Pattern - Bit 6
FAS Pattern - Bit 5
FAS Pattern - Bit 4
FAS Pattern - Bit 3
FAS Pattern - Bit 2
FAS Pattern - Bit 1
FAS Pattern - Bit 0
A Bit
N Bit
Figure 146 presents the typical behavior of the Re-
ceive Overhead Data Output Interface block, when
Method 1 is being used to sample the incoming E3
overhead bits.
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