XRT72L52 Datasheet, PDF (174/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52 TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.3
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PRELIMINARY
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1
BIT 0
Local Loopback
R/W
0
DS3/E3*
R/W
0
Internal LOS
Enable
R/W
1
RESET
R/W
0
Interrupt
Enable Reset
R/W
1
Frame Format
R/W
0
TimRefSel[1:0]
R/W
R/W
1
X
3. Interface the XRT72L52, to the Terminal Equip-
ment, as illustrated in Figure 48.
4.2.1.4 Mode 4 - The Nibble-Parallel/Loop-
Timed Mode Behavior of the XRT72L52
If the XRT72L52 has been configured to operate in
this mode, then the XRT72L52 will behave as follows.
A. Looped Timing (Uses the RxLineClk as the
Timing Reference)
In this mode, the Transmit Section of the XRT72L52
will use the RxLineClk signal as its timing reference.
When the XRT72L52 is operating in the Nibble-Mode,
it will internally divide the RxLineClk signal, by a fac-
tor of four (4) and will output this signal via the TxNib-
Clk output pin.
B. Nibble-Parallel Mode
The XRT72L52 will accept the DS3 payload data,
from the Terminal Equipment in a nibble-parallel man-
ner, via the TxNib[3:0] input pins. The Transmit Ter-
minal Equipment Input Interface block will latch this
data into its circuitry, on the rising edge of the TxNib-
Clk output signal.
C. Delineation of the outbound DS3 frames
The XRT72L52 will pulse the TxNibFrame output pin
"High" for one bit-period coincident with the
XRT72L52 processing the last nibble of a given DS3
frame.
D. Sampling of payload data, from the Terminal
Equipment
In Mode 4, the XRT72L52 will sample the data, at the
TxNib[3:0] input pins, on the third rising edge of the
RxOutClk clock signal, following a pulse in the TxNib-
Clk signal (see Figure 51).
NOTE: The TxNibClk signal, from the XRT72L52 operates
nominally at 11.184 MHz (e.g., 44.736 MHz divided by 4).
However, for reasons described below, TxNibClk effectively
operates at a "Low"er clock frequency. The Transmit Pay-
load Data Input Interface is only used to accept the payload
data, which is intended to be carried by outbound DS3
frames. The Transmit Payload Data Input Interface is not
designed to accommodate the entire DS3 data stream.
The DS3 Frame consists of 4704 payload bits or 1176
nibbles. Therefore, the XRT72L52 will supply 1176
TxNibClk pulses between the rising edges of two con-
secutive TxNibFrame pulses. The DS3 Frame repeti-
tion rate is 9.398kHz. Hence, 1176 TxNibClk pulses
for each DS3 frame period amounts to TxNibClk run-
ning at approximately 11.052 MHz. The method by
which the 1176 TxNibClk pulses are distributed
throughout the DS3 frame period is presented below.
Nominally, the Transmit Section within the XRT72L52
will generate a TxNibClk pulse for every 4 RxOutClk
(or TxInClk) periods. However, in 14 cases (within a
DS3 frame period), the Transmit Payload Data Input
Interface will allow 5 TxInClk periods to occur be-
tween two consecutive TxNibClk pulses.
Interfacing the Transmit Payload Data Input Inter-
face block of the XRT72L52 to the Terminal Equip-
ment for Mode 4 Operation
Figure 50 presents an illustration of the Transmit Pay-
load Data Input Interface block (within the XRT72L52)
being interfaced to the Terminal Equipment, for Mode
4 Operation.
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