XRT72L52 Datasheet, PDF (7/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
XRT72L52
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.3
BLOCK INTERRUPT STATUS REGISTER (ADDRESS = 0X05) ..................................................................... 128
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) ..................................................................... 129
TABLE 10: INTERRUPT SERVICE ROUTINE GUIDE (FOR DS3 APPLICATIONS) ........................................... 129
TABLE 11: INTERRUPT SERVICE ROUTINE GUIDE (FOR E3, ITU-T G.832 APPLICATIONS) ....................... 130
TABLE 12: INTERRUPT SERVICE ROUTINE GUIDE (FOR E3, ITU-T G.751 APPLICATIONS) ....................... 130
2.7.1 Automatic Reset of Interrupt Enable Bits .............................................................................................. 130
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ...................................................................... 131
2.7.2 One-Second Interrupts .......................................................................................................................... 131
2.8 INTERFACING THE FRAMER TO AN INTEL-TYPE MICROPROCESSOR ........................................................................ 131
TABLE 13: ALTERNATE FUNCTIONS OF PORT 3 PINS ............................................................................. 132
TABLE 14: INTERRUPT SERVICE ROUTINE LOCATION (IN CODE MEMORY) FOR THE INT0* AND INT1* INTERRUPT
INPUT PINS ............................................................................................................................................ 133
Figure 37. Schematic depicting how to interface the XRT72L52 DS3/E3 Framer IC to the 8051 Microcon-
troller ................................................................................................................................................... 133
2.9 INTERFACING THE FRAMER IC TO A MOTOROLA-TYPE MICROPROCESSOR ............................................................ 134
Figure 38. Schematic Depicting how to interface the XRT72L52 DS3/E3 Framer IC to the MC68000 Micro-
processor ............................................................................................................................................ 134
TABLE 15: AUTO-VECTOR TABLE FOR THE MC68000 MICROPROCESSOR .............................................. 135
3.0 The Line Interface and scan section ................................................................................................ 135
Figure 39. Schematic Depicting how to interface the XRT72L52 DS3/E3 Framer IC to the XRT73L02 DS3/
E3/STS-1 LIU IC (one channel shown) ............................................................................................... 136
3.1 BIT-FIELDS WITHIN THE LINE INTERFACE DRIVE REGISTER .................................................................................. 136
LINE INTERFACE DRIVE REGISTER (ADDRESS = 0X80) ..................................................................... 136
TABLE 16: THE RELATIONSHIP BETWEEN THE STATES OF RLOOP, LLOOP AND THE RESULTING LOOP-BACK MODE
WITH THE XRT7300 DEVICE .................................................................................................................. 138
3.2 BIT-FIELDS WITHIN THE LINE INTERFACE SCAN REGISTER ................................................................................... 138
LINE INTERFACE SCAN REGISTER (ADDRESS = 0X81) ...................................................................... 139
XRT72L52 CONFIGURATION ..................................................................................... 140
4.0 DS3 Operation of the XRT72L52 ...................................................................................................... 140
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ..................................................................... 140
4.1 DESCRIPTION OF THE DS3 FRAMES AND ASSOCIATED OVERHEAD BITS .............................................................. 140
Figure 40. DS3 Frame Format for C-bit Parity ................................................................................... 140
Figure 41. DS3 Frame Format for M13 .............................................................................................. 141
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ..................................................................... 141
TABLE 17: THE RELATIONSHIP BETWEEN THE CONTENT OF BIT 2, (C-BIT PARITY*/M13) WITHIN THE FRAMER OP-
ERATING MODE REGISTER AND THE RESULTING DS3 FRAMING FORMAT ................................................. 142
TABLE 18: C-BIT FUNCTIONS FOR THE C-BIT PARITY DS3 FRAME FORMAT ............................................ 142
4.1.1 Frame Synchronization Bits (Applies to both M13 and C-bit Parity Framing Formats) ......................... 142
4.1.2 Performance Monitoring/Error Detection Bits (Parity) ........................................................................... 143
4.1.3 Alarm and Signaling-Related Overhead Bits ......................................................................................... 143
Valid M-bits, F-bits, and P-bits ........................................................................................ 143
4.1.4 The Data Link Related Overhead Bits ................................................................................................... 144
4.2 THE TRANSMIT SECTION OF THE XRT72L52 (DS3 MODE OPERATION) ............................................................... 144
Figure 42. A Simple Illustration of the Transmit Section, within the XRT72L52, when it has been configured
to operate in the DS3 Mode ................................................................................................................ 145
4.2.1 The Transmit Payload Data Input Interface Block ................................................................................. 145
Figure 43. A Simple Illustration of the Transmit Payload Data Input Interface Block ......................... 146
TABLE 19: LISTING AND DESCRIPTION OF THE PINS ASSOCIATED WITH THE TRANSMIT PAYLOAD DATA INPUT IN-
TERFACE ............................................................................................................................................... 147
Figure 44. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data Input Inter-
face block (of the XRT72L52) for Mode 1(Serial/Loop-Timing) Operation .......................................... 149
Figure 45. Behavior of the Terminal Interface signals between the Transmit Payload Data Input Interface
block of the XRT72L52 and the Terminal Equipment (for Mode 1 Operation) .................................... 150
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ..................................................................... 150
Figure 46. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data Input Inter-
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