XRT72L52 Datasheet, PDF (376/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.3
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PRELIMINARY
referred to as the Frame Master and the Terminal Equip-
ment is referred to as the Frame Slave.
Finally, the XRT72L52 will pulse its TxOH_Ind output
pin, one bit-period prior to it processing a given over-
head bit, within the Outbound E3 frame. Since the
TxOH_Ind output pin of the XRT72L52 is electrically
connected to the E3_Overhead_Ind whenever the
XRT72L52 pulses the TxOH_Ind output pin "High", it
will also be driving the E3_Overhead_Ind input pin (of
the Terminal Equipment) "High". Whenever the Ter-
minal Equipment detects this pin toggling "High", it
should delay transmission of the very next DS3 frame
payload bit by one clock cycle.
The behavior of the signal between the XRT72L52
and the Terminal Equipment for E3 Mode 3 Operation
is illustrated in Figure 162.
FIGURE 162. BEHAVIOR OF THE TERMINAL INTERFACE SIGNALS BETWEEN THE XRT72L52 AND THE TERMINAL
EQUIPMENT (E3 MODE 3 OPERATION)
Terminal Equipment Signals
E3_Clock_In
E3_Data_Out
Tx_Start_of_Frame
E3_Overhead_Ind
Payload[4238] Payload[4239]
FA1, Bit 7
FA1, Bit 6
XRT72L5x Transmit Payload Data I/F Signals
TxInClk
TxSer
Payload[4238] Payload[4239]
TxFrame
TxOH_Ind
FA1, Bit 7
FA1, Bit 6
E3 Frame Number N
Note: TxFrame pulses high to denote
E3 Frame Boundary.
Note: TxOH_Ind pulses high for
16 bit periods in order to
denote Overhead Data
(e.g., the FA1 and FA2 bytes)
E3 Frame Number N + 1
Note: The FA1 byte will not be processed by the
Transmit Payload Data Input Interface.
How to configure the XRT72L52 to operate in this 2. Set the TimRefSel[1:0] bit-fields (within the
mode.
Framer Operating Mode Register) to "01".
1. Set the NibIntf input pin "Low".
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1
BIT 0
Local Loopback DS3/E3* Internal LOS
Enable
RESET
Interrupt Frame Format
Enable Reset
TimRefSel[1:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
1
0
1
0
0
0
3. Interface the XRT72L52, to the Terminal Equip-
ment, as illustrated in Figure 162.
6.2.1.4 Mode 4 - The Nibble-Parallel/Loop-
Timed Mode Behavior of the XRT72L52
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