XRT72L52 Datasheet, PDF (325/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
XRT72L52
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.3
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
RxLOF
Algo
RxLOF
RxOOF
RxLOS
RxAIS
Not Used
R/W
RO
RO
RO
RO
RO
RO
0
0
0
0
0
1
1
BIT 0
RxFERF
RO
1
When the Receive E3 Framer block is operating in the
In-Frame state, it will then begin to perform Frame
Maintenance operations, where it will continue to ver-
ify that the Frame Alignment signal (FAS pattern) is
present, and at its proper location. While the Receive
E3 Framer block is operating in the Frame Mainte-
nance Mode, it will declare an Out-of-Frame (OOF)
Condition if it detects an invalid FAS pattern in four
consecutive frames.
Since the Receive E3 Framer block requires the de-
tection of an invalid FAS pattern in four consecutive
frames, in order for it to transition to the OOF Condi-
tion state, it can tolerate some errors in the Framing
Alignment bytes, and still remain in the In-Frame
state. However, each time the Receive E3 Framer
block detects an error in the FAS pattern, it will incre-
ment the PMON Framing Error Event Count Regis-
ters (Address = 0x52 and 0x53). The bit-format for
these two registers are depicted below.
PMON FRAMING BIT/BYTE ERROR COUNT REGISTER - MSB (ADDRESS = 0X52)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
Framing Bit/Byte Error Count - High Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
BIT 0
RUR
0
PMON FRAMING BIT/BYTE ERROR COUNT REGISTER - LSB (ADDRESS = 0X53)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
Framing Bit/Byte Error Count - Low Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
BIT 0
RUR
0
5.3.2.3 Forcing a Reframe via Software Com-
mand
The XRT72L52 Framer IC permits the user to com-
mand a reframe procedure with the Receive E3 Fram-
er block via software command. If the user writes a
“1” into Bit 0 (Reframe) within the I/O Control Register
(Address = 0x01), as depicted below, then the Re-
ceive E3 Framer block will be forced into the FAS Pat-
tern Search state, per Figure 138., and will begin its
search for the FAS Pattern.
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