XRT72L52 Datasheet, PDF (46/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.3
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PRELIMINARY
AC ELECTRICAL CHARACTERISTICS (CONT.)
Test Conditions: TA = 25°C, VDD = 3.3V + 5% unless otherwise specified
SYMBOL
PARAMETER
MIN. TYP.
t₂₇ TxInClk clock (falling) edge to TxOHIns hold-time
0
0
MAX.
UNITS
CONDITIONS
ns DS3 Applications
ns E3, ITU-T G.832
Applications
0
t₂₈ TXOHIns to TxInClk (falling edge) set-up Time
254
72
ns E3, ITU-T G.751
Applications
ns DS3 Applications
ns E3, ITU-T G.832
Applications
15
t₂₉ TxInClk clock (falling) edge to TxOHIns hold-time
0
0
ns E3, ITU-T G.751
Applications
ns DS3 Applications
ns E3, ITU-T G.832
Applications
t_29A TxOHEnable to TxOHIns/TxOH Delay
Transmit LIU Interface Timing (see Figure 9 and Figure 10)
t₃₀ Rising edge of TxLineClk to rising edge of TxPOS
or TxNEG output signal.
(Framer is configured to output data on TxPOS and
TxNEG on rising edge of TxLineClk
t₃₁ Falling edge of TxLineClk to rising edge of TxPOS or
TxNEG
(Framer is configured to output data via TxPOS and
TxNEG on falling edge of TxLineClk)
f_TxLineClk Period of TxLineClk clock signal
f_TxLineClk Period of TxLineClk clock signal
t₃₂ Period of TxLineClk
t32 Period of TxLineClk
Receive LIU Interface Timing (see Figure 11 and Figure 12)
t₃₈ RxPOS or RxNEG set-up time to rising edge of
RxLineClk.
(Framer is configured to sample data on RxPOS and
RxNEG input pins, on the rising edge of RxLineClk)
t₃₉ RxPOS or RxNEG hold time, from rising edge of
RxLineClk
(Framer is configured to sample data on RxPOS and
RxNEG input pins, on the rising edge of RxLineClk)
0
1
2.0
2.4
44.736
34.368
22.36
29.10
0
4
ns E3, ITU-T G.751
Applications
ns
ns
ns
MHz DS3 Applications
Mhz E3 Applications
ns DS3 Applications
ns E3 Applications
ns
ns
27