XRT72L52 Datasheet, PDF (277/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
XRT72L52
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.3
3. Interface the XRT72L52, to the Terminal Equip-
ment, as illustrated in Figure 104.
5.2.1.4 Mode 4 - The Nibble-Parallel/Loop-
Timed Mode Behavior of the XRT72L52
If the XRT72L52 has been configured to operate in
this mode, then the XRT72L52 will behave as follows.
A. Looped Timing (Uses the RxLineClk as the
Timing Reference)
In this mode, the Transmit Section of the XRT72L52
will use the RxLineClk signal as its timing reference.
When the XRT72L52 is operating in the Nibble-Mode,
it will internally divide the RxLineClk signal, by a fac-
tor of four (4) and will output this signal via the TxNib-
Clk output pin.
B. Nibble-Parallel Mode
The XRT72L52 will accept the E3 payload data, from
the Terminal Equipment in a nibble-parallel manner,
via the TxNib[3:0] input pins. The Transmit Terminal
Equipment Input Interface block will latch this data in-
to its circuitry, on the rising edge of the TxNibClk out-
put signal.
C. Delineation of the outbound E3 frames
The XRT72L52 will pulse the TxNibFrame output pin
"High" for one bit-period coincident with the
XRT72L52 processing the last nibble of a given E3
frame.
D. Sampling of payload data, from the Terminal
Equipment
In Mode 4, the XRT72L52 will sample the data, at the
TxNib[3:0] input pins, on the third rising edge of the
RxOutClk clock signal, following a pulse in the TxNib-
Clk signal (see Figure 107).
NOTE: The TxNibClk signal, from the XRT72L52 operates
nominally at 8.592 MHz (e.g., 34.368 MHz divided by 4).
The E3 Frame consists of 1536 bits or 384 nibbles.
Therefore, the XRT72L52 will supply 384 TxNibClk
pulses between the rising edges of two consecutive
TxNibFrame pulses. The E3 Frame repetition rate is
22.375kHz. Hence, 384 TxNibClk pulses for each E3
frame period amounts to TxNibClk running at approx-
imately 8.592 MHz. The method by which the 384
TxNibClk pulses are distributed throughout the E3
frame period is presented below.
Nominally, the Transmit Section within the XRT72L52
will generate a TxNibClk pulse for every 4 RxOutClk
(or TxInClk) periods.
Interfacing the Transmit Payload Data Input Inter-
face block of the XRT72L52 to the Terminal Equip-
ment for Mode 4 Operation
Figure 106 presents an illustration of the Transmit
Payload Data Input Interface block (within the
XRT72L52) being interfaced to the Terminal Equip-
ment, for Mode 4 Operation.
FIGURE 106. ILLUSTRATION OF THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT PAYLOAD DATA
INPUT INTERFACE BLOCK OF THE XRT72L52 FOR MODE 4 (NIBBLE-PARALLEL/LOOP-TIMED) OPERATION
E3_Nib_Clock_In
E3_Data_Out[3:0]
Tx_Start_of_Frame
E3_Overhead_Ind
8.592 MHz
4
TxNibClk
TxNib[3:0]
TxNibFrame
TxOH_Ind
VCC
NibInt
RxLineClk
34.368MHz
Terminal Equipment
XRT72L5x E3 Framer
Mode 4 Operation of the Terminal Equipment
When the XRT72L52 is operating in this mode, it will
function as the source of the 8.592MHz (e.g., the
34.368MHz clock signal divided by 4) clock signal,
that will be used as the Terminal Equipment Interface
clock by both the XRT72L52 and the Terminal Equip-
ment.
The Terminal Equipment will output the payload data
of the outbound E3 data stream via its
E3_Data_Out[3:0] pins on the rising edge of the
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