XRT72L52 Datasheet, PDF (24/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.3
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PRELIMINARY
PIN DESCRIPTION
PIN #
15
PIN NAME
RxOutClk[0]/
RxHDLCDat7[0]
16
TxNEG[0]
17
TxPOS[0]
18
TxLineClk[0]
19
VDD
TYPE
O
O
O
O
****
DESCRIPTION
Receive Out Clock - Transmit Terminal Interface Clock for Loop-
Timing:
This clock signal functions as the "Terminal Interface" clock source, if
the XRT72L52 Framer IC is operating in the "loop-timing" mode.
In this mode, the Transmitting Terminal Equipment is expected to input
data to the Framer IC, via the “TxSer” input pin, upon the rising edge of
this clock signal. The XRT72L52 will use the rising edge of this clock
signal to sample the data at the TxSer input.
This clock signal is a buffered version of the RxLineClk signal.
Receive HDLC Data Output - 7:
This pin contains bit 7 RxHDLC data when the HDLC controller is on.
Transmit Negative Polarity Pulse:
The exact role of this output pin depends upon whether the Framer is
operating in the Unipolar or Bipolar Mode.
Unipolar Mode:
This output signal pulses "high" for one bit period, at the end of each
"outbound" DS3 or E3 frame. This output signal is at a logic "low" for all
of the remaining bit-periods of the "outbound" DS3 or E3 frames
Bipolar Mode:
This output pin functions as one of the two dual-rail output signals that
commands the sequence of pulses to be driven on the line. TxPOS is
the other output pin. This input is typically connected to the TNDATA
input of the external DS3/E3 Line Interface Unit IC. When this output is
asserted, it will command the LIU to generate a negative polarity pulse
on the line.
Transmit Positive Polarity Pulse:
The exact role of this output pin depends upon whether the Framer is
operating in the Unipolar or Bipolar Mode.
Unipolar Mode:
This output pin functions as the "Single-Rail" output signal for the "out-
bound" DS3 or E3 data stream. The signal, at this output pin, will be
updated on the "user-selected" edge of the TxLineClk signal.
Bipolar Mode:
This output pin functions as one of the two dual rail output signals that
commands the sequence of pulses to be driven on the line. TxNEG is
the other output pin. This input is typically connected to the TPDATA
input of the external DS3 or E3 Line Interface Unit IC. When this output
is asserted, it will command the LIU to generate a positive polarity pulse
on the line
Transmit Line Interface Clock:
This clock signal is output to the Line Interface Framer, along with the
TxPOS and TxNEG signals. The purpose of this output clock signal is to
provide the LIU with timing information that it can use to generate the
AMI pulses and deliver them over the transmission medium to the Far-
End Receiver. The user can configure the source of this clock to be
either the RxLineClk (from the Receiver portion of the Framer) or the
TxInClk input. The nominal frequency of this clock signal is 34.368
MHz.
Power Supply 3.3V + 5%
5