XRT72L52 Datasheet, PDF (12/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.3
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PRELIMINARY
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) ..................................................................... 241
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) ..................................................................... 241
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) ..................................................................... 241
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) ..................................................................... 242
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) ..................................................................... 242
RXDS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17) ............................................. 243
RXDS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17) ............................................. 243
RXDS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17) ............................................. 244
RXDS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17) ............................................. 244
RXDS3 LAPD CONTROL REGISTER (ADDRESS = 0X18) ......................................................................... 245
RXDS3 LAPD CONTROL REGISTER (ADDRESS = 0X18) ......................................................................... 245
5.0 E3/ITU-T G.751 Operation of the XRT72L52 ..................................................................................... 246
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ..................................................................... 246
5.1 DESCRIPTION OF THE E3, ITU-T G.751 FRAMES AND ASSOCIATED OVERHEAD BITS ........................................... 246
Figure 97. Illustration of the E3, ITU-T G.751 Framing Format. ......................................................... 246
5.1.1 Definition of the Overhead Bits .............................................................................................................. 246
5.2 THE TRANSMIT SECTION OF THE XRT72L52 (E3, ITU-T G.751 MODE OPERATION) ............................................ 247
Figure 98. A Simple Illustration of the XRT72L52 Transmit Section when it has been configured to operate
in the E3 Mode .................................................................................................................................... 247
5.2.1 The Transmit Payload Data Input Interface Block ................................................................................. 247
Figure 99. A Simple Illustration of the Transmit Payload Data Input Interface Block ......................... 248
TABLE 47: LISTING AND DESCRIPTION OF THE PINS ASSOCIATED WITH THE TRANSMIT PAYLOAD DATA INPUT IN-
TERFACE ............................................................................................................................................... 249
Figure 100. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data Input In-
terface block of the XRT72L52 for Mode 1 (Serial/Loop-Timed) Operation ........................................ 250
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30) ............................................................................ 251
Figure 101. Behavior of the Terminal Interface signals between the XRT72L52 Transmit Payload Data Input
Interface block and the Terminal Equipment (for Mode 1 Operation) .................................................. 253
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ..................................................................... 253
Figure 102. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data Input In-
terface block of the XRT72L52 for Mode 2 (Serial/Local-Timed/Frame-Slave) Operation .................. 254
Figure 103. Behavior of the Terminal Interface signals between the XRT72L52 and the Terminal Equipment
(Mode 2 Operation) ............................................................................................................................. 255
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ..................................................................... 255
Figure 104. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data Input In-
terface block of the XRT72L52 for Mode 3 (Serial/Local-Time/Frame-Master) Operation .................. 256
Figure 105. Behavior of the Terminal Interface signals between the XRT72L52 and the Terminal Equipment
(E3 Mode 3 Operation) ........................................................................................................................ 257
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ..................................................................... 257
Figure 106. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data Input In-
terface block of the XRT72L52 for Mode 4 (Nibble-Parallel/Loop-Timed) Operation .......................... 258
Figure 107. Behavior of the Terminal Interface signals between the XRT72L52 and the Terminal Equipment
(Mode 4 Operation) ............................................................................................................................. 259
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ..................................................................... 259
Figure 108. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data Input In-
terface block of the XRT72L52 for Mode 5 (Nibble-Parallel/Local-Timed/Frame-Slave) Operation .... 261
Figure 109. Behavior of the Terminal Interface signals between the XRT72L52 and the Terminal Equipment
(E3, Mode 5 Operation) ....................................................................................................................... 262
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ..................................................................... 262
Figure 110. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data Input In-
terface block of the XRT72L52 for Mode 6 (Nibble-Parallel/Local-Timed/Frame-Master) Operation .. 263
Figure 111. Behavior of the Terminal Interface signals between the XRT72L52 and the Terminal Equipment
(E3 Mode 6 Operation) ........................................................................................................................ 264
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ..................................................................... 264
5.2.2 The Transmit Overhead Data Input Interface ........................................................................................ 264
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