XRT72L52 Datasheet, PDF (216/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52 TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.3
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PRELIMINARY
II/O CONTROL REGISTER (ADDRESS = 0X01)
BIT 7
BIT 6
BIT 5
BIT 4
Disable TxLOC
R/W
1
LOC
RO
0
Disable
RxLOC
R/W
1
AMI/ZeroSup*
R/W
0
Table 36 relates the value of this bit-field to the Re-
ceive DS3 LIU Interface Input Mode.
BIT 3
Unipolar/
Bipolar*
R/W
0
BIT2
TxLine CLK
Invert
R/W
0
BIT 1
RxLine CLK
Invert
R/W
0
BIT 0
Reframe
R/W
0
TABLE 36: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TXLINECLK INV) WITHIN THE I/O CONTROL
REGISTER AND THE TXLINECLK CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON
BIT 3
0
1
RECEIVE DS3 LIU INTERFACE INPUT MODE
.Bipolar Mode (Dual Rail): AMI or B3ZS Line Codes are Transmitted and Received.
Unipolar Mode (Single Rail) Mode of transmission and reception of DS3 data is selected.
NOTES:
1. The default condition is the Bipolar Mode.
2. This selection also effects the Transmit DS3 Framer
Line Interface Output Mode
4.3.1.2 Bipolar Decoding
If the Receive DS3 LIU Interface block is operating in
the Bipolar Mode, then it will receive the DS3 data
pulses via both the RxPOS, RxNEG, and the RxLi-
neClk input pins. Figure 75 presents a circuit dia-
gram illustrating how the Receive DS3 LIU Interface
block interfaces to the Line Interface Unit while the
Framer is operating in Bipolar mode. The Receive
DS3 LIU Interface block can be configured to decode
the incoming data from either the AMI or B3ZS line
codes.
FIGURE 75. ILLUSTRATION ON HOW THE RECEIVE DS3 FRAMER (WITHIN THE XRT72L52 FRAMER IC) BEING INTER-
FACED TO THEXRT7302 LIU, WHILE THE FRAMER IS OPERATING IN BIPOLAR MODE (ONE CHANNEL SHOWN)
Rx_AIS_Ch_0
RxRED_ALARM_0
Rx_OOF_Ch_0
RxLOS_Ch_0
RxFRAME_0
RxSER_CLK_0
RxDATA_IN_0
D[7:0]
A[9:0]
READY_OUT*
ALE
RD*
WR*
XRT72L52_CS*
XRT72L52_INT*
HW_RESET*
TxFRAME_0
44.736MHz
TxDATA_OUT
RxAVDD_0
DVDD_0
U1
160
159
RxAIS_0
2
3
RxRED_0
RxOOF_0
RxLOS_0
122
126
125
89
RxFrame_0
RxClk_0
RxSer_0
MOTO
RxPOS_0 ²³
RxNEG_0 ²¹
113
112
111
D7
D6
110
108
107
106
105
D5
D4
D3
D2
D1
D0
RxLineClk_0 ²⁴
152
RLOL_0
ExtLOS_0
151
103
102
101
100
99
98
A9
A8
A7
A6
A5
97
96
95
94
A4
A3
A2
A1
A0
115
92
85
91
Rdy_Dtck
ALE_AS
RDB_DS
90
116
WRB_RW
CS
INT
88 _RESET
LLOOP_0
REQB_0
TAOS_0
DMO_0
TxLEV_0
156
157
158
150
5
RLOOP_0 ¹⁵⁵
ENCODIS_0 (TxOFF_0) ⁴
TxPOS_0 ¹⁷
TxNEG_0 ¹⁶
TxLineClk_0 ¹⁸
87 _NIBBLEINTF
128
22
133
TxFrame_0
TxInClk_0
TxSer_0
XRT72L52_Ch_0
C2
0.01uF
C3
0.01uF
R7
4.7k
26 _RxAVDD0
7 _RxDVDD0
23
8
LOSTHR_0
HOST/HW
11 _RPOS0
10 _RNEG0
9 _RCLK0
U2
TxAVDD0 ³
TxAVDD0 ⁷⁴
RTIP0 ²⁸
RRING0 ²⁷
XRT71D00_CS* (Optional)
15
13
RLOL_0
RLOS_0
17
18
19
20
42
CS
SCLK
SDI
SDO
REG_RESET*
80 _{TxOFF_0}
78 _{TPDATA_0}
77 _{TNDATA_0}
79
16
TCLK_0
EXCLK_0
12 _RxDGND0
29 _RxAGND0
TTIP0 ⁷³
TRING0 ⁷²
MTIP0 ⁷⁶
MRING0 ⁷⁵
TxAGND0 ⁷¹
TxAGND0 ⁵
XRT73L02IV
C4
0.01uF
C5
0.01uF
TxAVDD
R1
R2
37.4
37.4
C1
0.01uF
6 _T2 1
4
3
T3001
R3
31.6
R4
R5
31.6
270
R6
270
1 _T1 6
3
4
T3001
J1
BNC
1
J2
BNC
1
197