XRT72L52 Datasheet, PDF (171/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L52
REV. P1.1.3
NOTES:
1. In this case, the Terminal Equipment is controlling
the start of Frame Generation, and is therefore
referred to as the Frame Master. Conversely, since
the XRT72L52 does not control the generation of a
new DS3 frame, but is rather driven by the Terminal
Equipment. Hence, the XRT72L52 is referred to as
the Frame Slave.
2. If the user opts to configure the XRT72L52 to oper-
ate in Mode 2, it is imperative that the
Tx_Start_of_Frame (or TxFrameRef) signal is syn-
chronized to the TxInClk input clock signal.
Finally, the XRT72L52 will pulse its TxOH_Ind output
pin, one bit-period prior to it processing a given over-
head bit, within the outbound DS3 frame. Since the
TxOH_Ind output pin of the XRT72L52 is electrically
connected to the DS3_Overhead_Ind, whenever the
XRT72L52 pulses the TxOH_Ind output pin "High", it
will also be driving the DS3_Overhead_Ind input pin
(of the Terminal Equipment) "High". Whenever the
Terminal Equipment detects this pin toggling "High", it
should delay transmission of the very next DS3 frame
payload bit by one clock cycle.
The behavior of the signals between the XRT72L52
and the Terminal Equipment for DS3 Mode 2 Opera-
tion is illustrated in Figure 47.
FIGURE 47. BEHAVIOR OF THE TERMINAL INTERFACE SIGNALS BETWEEN THE XRT72L52 AND THE TERMINAL
EQUIPMENT (MODE 2 OPERATION)
Terminal Equipment Signals
DS3_Clock_In
DS3_Data_Out
Tx_Start_of_Frame
DS3_Overhead_Ind
Payload[4702] Payload[4703]
X-Bit
Payload[1]
XRT72L5x Transmit Payload Data I/F Signals
TxInClk
TxSer
Payload[4702] Payload[4703]
TxFrameRef
TxOH_Ind
X-Bit
Payload[1]
DS3 Frame Number N
DS3 Frame Number N + 1
Note: X-Bit will not be processed by the
Note: TxOH_Ind pulses high to
Transmit Payload Data Input Interface.
denote Overhead Data
(e.g., the X-bit).
Note: TxFrame pulses high to denote
DS3 Frame Boundary.
How to configure the XRT72L52 to operate in this
mode.
1. Set the NibIntf input pin "Low".
2. Set the TimRefSel[1:0] bit-fields (within the
Framer Operating Mode Register) to "01" as
depicted below.
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00)
BIT 7
Local Loopback
R/W
BIT 6
DS3/E3*
R/W
BIT 5
Internal LOS
Enable
R/W
BIT 4
RESET
R/W
BIT 3
Interrupt
Enable Reset
R/W
BIT2
Frame Format
R/W
BIT 1
BIT 0
TimRefSel[1:0]
R/W
R/W
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