XRT72L52 Datasheet, PDF (15/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
XRT72L52
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.3
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11) ...................................................... 309
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11) ...................................................... 309
RXE3 CONFIGURATION & STATUS REGISTER - 1 G.751 (ADDRESS = 0X10) ........................................... 310
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15) ................................................................. 310
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11) ...................................................... 310
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11) ...................................................... 311
Figure 138. Illustration of the Local Receive E3 Framer block, receiving an E3 Frame (from the Remote
Terminal) with a correct BIP-4 Value. ................................................................................................. 311
Figure 139. Illustration of the Local Receive E3 Framer block, transmitting an E3 Frame (to the Remote
Terminal) with the “A” bit set to “0” ...................................................................................................... 312
Figure 140. Illustration of the Local Receive E3 Framer block, receiving an E3 Frame (from the Remote
Terminal) with an incorrect BIP-4 value. ............................................................................................. 313
Figure 141. Illustration of the Local Receive E3 Framer block, transmitting an E3 Frame (to the Remote
Terminal) with the “A” bit-field set to “1” .............................................................................................. 313
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15) ................................................................. 314
PMON PARITY ERROR COUNT REGISTER - MSB (ADDRESS = 0X54) ..................................................... 314
PMON PARITY ERROR COUNT REGISTER - LSB (ADDRESS = 0X55) ...................................................... 314
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30) ............................................................................ 314
RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13) ................................................................. 315
5.3.3 The Receive HDLC Controller Block ..................................................................................................... 315
Figure 142. LAPD Message Frame Format ....................................................................................... 316
RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18 ............................................................................ 316
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) .............................................................................. 317
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) .............................................................................. 317
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) .............................................................................. 318
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) .............................................................................. 318
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) .............................................................................. 318
TABLE 63: THE RELATIONSHIP BETWEEN THE CONTENTS OF RXLAPDTYPE[1:0] BIT-FIELDS AND THE PMDL MES-
SAGE TYPE/SIZE ................................................................................................................................... 319
RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18 ............................................................................ 319
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) .............................................................................. 319
Figure 143. Flow Chart depicting the Functionality of the LAPD Receiver ........................................ 320
5.3.4 The Receive Overhead Data Output Interface ...................................................................................... 320
Figure 144. A Simple Illustration of the Receive Overhead Output Interface block ........................... 321
Figure 145. Illustration of how to interface the Terminal Equipment to the Receive Overhead Data Output
Interface block (for Method 1). ............................................................................................................ 322
TABLE 64: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT
INTERFACE BLOCK (FOR METHOD 1) ..................................................................................................... 323
TABLE 65: THE RELATIONSHIP BETWEEN THE NUMBER OF RISING CLOCK EDGES IN RXOHCLK, (SINCE RXO-
HFRAME WAS LAST SAMPLED "HIGH”) TO THE E3 OVERHEAD BIT, THAT IS BEING OUTPUT VIA THE RXOH OUTPUT
PIN ....................................................................................................................................................... 323
Figure 146. Illustration of the signals that are output via the Receive Overhead Output Interface (for Method
1). ........................................................................................................................................................ 324
TABLE 66: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT
INTERFACE BLOCK (METHOD 2) ............................................................................................................. 325
Figure 147. Illustration of how to interface the Terminal Equipment to the Receive Overhead Data Output
Interface block (for Method 2). ............................................................................................................ 326
TABLE 67: THE RELATIONSHIP BETWEEN THE NUMBER OF RXOHENABLE OUTPUT PULSES (SINCE RXOHFRAME
WAS LAST SAMPLED "HIGH") TO THE E3 OVERHEAD BIT, THAT IS BEING OUTPUT VIA THE RXOH OUTPUT PIN ..
327
Figure 148. Illustration of the signals that are output via the Receive Overhead Data Output Interface block
(for Method 2). ..................................................................................................................................... 327
5.3.5 The Receive Payload Data Output Interface ......................................................................................... 328
Figure 149. A Simple illustration of the Receive Payload Data Output Interface block ...................... 328
TABLE 68: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE PAYLOAD DATA OUTPUT IN-
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