XRT72L52 Datasheet, PDF (33/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
PIN DESCRIPTION
PIN #
122
PIN NAME
RxFrame[0]
123
VDD
124
RxOHInd[0]
125
RxSer[0]/
RxIdle[0]
XRT72L52
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.3
TYPE
O
****
O
O
DESCRIPTION
Receive Boundary of DS3 or E3 Frame Output Indicator:
The exact functionality of this output pin depends upon whether the
XRT72L52 Framer IC is operating in the “Serial” or “Nibble-Parallel”
Mode.
Serial Mode Operation:
The Receive Section of the XRT72L52 will pulse this output pin “high”
(for one bit-period) when the “Receive Payload Data Output Interface”
block is driving the very first bit of a given DS3 or E3 frame, onto the
“RxSer” output pin.
Nibble-Parallel Operation:
The Receive Section of the XRT72L52 will pulse this output pin “high”
(for one nibble-period), when the “Receive Payload Data Output Inter-
face” block is driving the very first nibble of a given DS3 or E3 frame,
onto the “RxNib[3:0] output pins.
Power Supply 3.3V + 5%
Receive Overhead Bit Indicator:
The exact functionality of this output pin depends upon whether the
XRT72L52 Framer IC is operating in the “Serial” or “Nibble-Parallel”
Mode.
Serial Mode Operation:
This output pin pulses "high" (for one bit-period) whenever an "over-
head" bit is being output via the "RxSer" output pin, by the "Receive
Payload Data Output Interface" block.
Nibble-Parallel Mode Operation:
This output pin pulses “high” (for one nibble-period) whenever an “over-
head” nibble is being output via the “RxNib[3:0] output pins, by the
“Receive Payload Data Output Interface” block.
NOTE: The purpose of this output pin is to alert the "Receive Terminal
Equipment" that an overhead bit is being output via the "RxSer" output
pin, and that this data should be ignored.
Receive Serial Output:
If the user opts to operate the XRT72L52 in the "serial" mode, then the
chip will output the payload data, of the incoming DS3 or E3 frames, via
this pin. The XRT72L52 will output this data upon the rising edge of
RxClk.
The user is advised to design the Terminal Equipment such that it will
sample this data on the falling edge of RxClk.
NOTE: This signal is only active if the "NibInt" input pin is pulled "low".
Receive Idle:
This pin will go high indicating the idle period of sent HDLC data pack-
ets. Also, in combination with ValFCS it can indicate error conditions.
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