EP2C8T144I8N Datasheet, PDF (74/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

I/O Structure & Features
Figure 2–27. DDR SDRAM Interfacing
DQS
DQ
OE
LE
Register
LE
Register
VCC
LE
Register
OE
LE
Register
t
LE
Register
DataA
LE
Register
LE
Register
Adjacent LAB LEs
LE
Register
PLL
GND
LE
Register
clk
-90˚ Shifted clk
Clock Delay
Control Circuitry
DataB
LE
Register
en/dis
Global Clock
Clock Control
Block
ENOUT
Dynamic Enable/Disable
Circuitry
ena_register_mode
LE
Register
LE
Register
LE
Register
Resynchronizing
to System Clock
f
For more information on Cyclone II external memory interfaces, see the
External Memory Interfaces chapter in Volume 1 of the Cyclone II Device
Handbook.
2–48
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007