EP2C8T144I8N Datasheet, PDF (261/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

External Memory Interfaces
Figure 9–4. CQ & CQn Connection for QDRII SRAM Read
dataout_h
LE
Register
sync_reg_l
LE
Register
Input Register AI
dataout_l
LE
Register
sync_reg_h
neg_reg_out
LE
LE
Register
Register
Register CI
Input Register BI
resynch_clk
DQ
Dt
DQS/CQ# (CQn)
Clock Delay
Control Circuitry
Dt
DQS/CQ (CQ)
Read & Write Operation
Figure 9–5 shows the data and clock relationships in QDRII SRAM
devices at the memory pins during reads. QDRII SRAM devices send data
within t_CO time after each rising edge of the read clock C or C# in multi-
clock mode or the input clock K or K# in single clock mode. Data is valid
until t_DOH time after each rising edge of the read clock C or C# in multi-
clock mode or the input clock K or K# in single clock mode. The CQ and
CQn clocks are edge-aligned with the read data signal. These clocks
accompany the read data for data capture in Cyclone II devices.
Altera Corporation
February 2007
9–7
Cyclone II Device Handbook, Volume 1