EP2C8T144I8N Datasheet, PDF (244/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Clock Modes
Figure 8–16. Cyclone II Input/Output Clock Mode in Single-Port Mode Notes (1), (2)
6 LAB Row
Clocks
6
data[ ]
DQ
ENA
Memory Block
256 ´ 16
Data In _{512 ´ 8}
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
address[ ]
DQ
ENA
Address
byteena[ ]
DQ
ENA
Data Out
Byte Enable
DQ
ENA
addressstall
Address
Clock Enable
wren
outclocken
inclocken
inclock
outclock
DQ
ENA
Write
Pulse
Generator
Write Enable
To MultiTrack
Interconnect (2)
Notes to Figure 8–16:
(1) Violating the setup or hold time on the memory block address registers could corrupt memory contents. This applies
to both read and write operations.
(2) For more information about the MultiTrack interconnect, refer to Cyclone II Device Family Data Sheet in volume 1 of
the Cyclone II Device Handbook.
Read/Write Clock Mode
Cyclone II memory blocks can implement read/write clock mode for
simple dual-port memory. The write clock controls the blocks’ data
inputs, write address, and write enable signals. The read clock controls
the data output, read address, and read enable signals. The memory
blocks support independent clock enables for each clock for the read- and
write-side registers. This mode does not support asynchronous clear
signals for the registers. Figure 8–17 shows a memory block in read/write
clock mode.
8–22
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2008