|
EP2C8T144I8N Datasheet, PDF (6/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1 | |||
|
◁ |
Contents
clkena signals .................................................................................................................................. 7â29
Board Layout ........................................................................................................................................ 7â30
VCCA & GNDA ............................................................................................................................. 7â31
VCCD & GND ................................................................................................................................. 7â33
Conclusion ............................................................................................................................................ 7â33
Section III. Memory
Revision History .................................................................................................................................... 7â1
Chapter 8. Cyclone II Memory Blocks
Introduction ............................................................................................................................................ 8â1
Overview ................................................................................................................................................. 8â1
Control Signals .................................................................................................................................. 8â3
Parity Bit Support ............................................................................................................................. 8â4
Byte Enable Support ........................................................................................................................ 8â4
Packed Mode Support ..................................................................................................................... 8â6
Address Clock Enable ...................................................................................................................... 8â6
Memory Modes ...................................................................................................................................... 8â8
Single-Port Mode .............................................................................................................................. 8â9
Simple Dual-Port Mode ................................................................................................................. 8â10
True Dual-Port Mode ..................................................................................................................... 8â12
Shift Register Mode ........................................................................................................................ 8â14
ROM Mode ...................................................................................................................................... 8â16
FIFO Buffer Mode ........................................................................................................................... 8â16
Clock Modes ......................................................................................................................................... 8â16
Independent Clock Mode .............................................................................................................. 8â17
Input/Output Clock Mode ........................................................................................................... 8â19
Read/Write Clock Mode ............................................................................................................... 8â22
Single-Clock Mode ......................................................................................................................... 8â24
Power-Up Conditions & Memory Initialization ........................................................................ 8â27
Read-During- Write Operation at the Same Address .................................................................... 8â28
Same-Port Read-During-Write Mode .......................................................................................... 8â28
Mixed-Port Read-During-Write Mode ........................................................................................ 8â29
Conclusion ............................................................................................................................................ 8â30
Referenced Documents ....................................................................................................................... 8â30
Chapter 9. External Memory Interfaces
Introduction ............................................................................................................................................ 9â1
External Memory Interface Standards ................................................................................................ 9â2
DDR & DDR2 SDRAM .................................................................................................................... 9â2
QDRII SRAM ..................................................................................................................................... 9â5
Cyclone II DDR Memory Support Overview .................................................................................... 9â9
Data & Data Strobe Pins ................................................................................................................ 9â10
Clock, Command & Address Pins ............................................................................................... 9â14
Parity, DM & ECC Pins ................................................................................................................. 9â14
vi
Cyclone II Device Handbook, Volume 1
Altera Corporation
|
▷ |