EP2C8T144I8N Datasheet, PDF (187/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

PLLs in Cyclone II Devices
Figure 7–1. Cyclone II Device PLL Locations
PLL
I/O Bank 3
3
Note (1)
CLK[8..11]
I/O Bank 4
I/O Bank 2
GCLK[8..11]
PLL
2
I/O Bank 5
CLK[0..3]
GCLK[0..3]
GCLK[4..7]
CLK[4..7]
I/O Bank 1
GCLK[12..15]
I/O Bank 6
PLL
I/O Bank 8
1
I/O Bank 7
PLL
4
CLK[12..15]
Note to Figure 7–1:
(1) This figure shows the PLL and clock inputs in the EP2C15 through EP2C70 devices. The EP2C5 and EP2C8 devices
only have eight global clocks (CLK[0..3] and CLK[4..7]) and PLLs 1 and 2.
The main purpose of a PLL is to synchronize the phase and frequency of
the VCO to an input reference clock. There are a number of components
that comprise a PLL to achieve this phase alignment.
The PLL compares the rising edge of the reference input clock to a
feedback clock using a phase-frequency detector (PFD). The PFD
produces an up or down signal that determines whether the VCO needs
to operate at a higher or lower frequency. The PFD output is applied to
the charge pump and loop filter, which produces a control voltage for
setting the frequency of the VCO. If the PFD transitions the up signal
high, then the VCO frequency increases. If the PFD transitions the down
signal high, then the VCO frequency decreases.
Altera Corporation
February 2007
7–3
Cyclone II Device Handbook, Volume 1