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EP2C8T144I8N Datasheet, PDF (72/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1 | |||
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I/O Structure & Features
Figure 2â26. Cyclone II Device DQ & DQS Groups in Ã8/Ã9 Mode Notes (1), (2)
DQ Pins
DQS Pin (2)
DQ Pins
Notes to Figure 2â26:
(1) Each DQ group consists of a DQS pin, DM pin, and up to nine DQ pins.
(2) This is an idealized pin layout. For actual pin layout, refer to the pin table.
DM Pin
Cyclone II devices support the data strobe or read clock signal (DQS)
used in DDR and DDR2 SDRAM. Cyclone II devices can use either
bidirectional data strobes or unidirectional read clocks. The dedicated
external memory interface in Cyclone II devices also includes
programmable delay circuitry that can shift the incoming DQS signals to
center align the DQS signals within the data window.
The DQS signal is usually associated with a group of data (DQ) pins. The
phase-shifted DQS signals drive the global clock network, which is used
to clock the DQ signals on internal LE registers.
Table 2â15 shows the number of DQ pin groups per device.
Table 2â15. Cyclone II DQS & DQ Bus Mode Support (Part 1 of 2) Note (1)
Device
EP2C5
EP2C8
EP2C15
EP2C20
Package
144-pin TQFP (2)
208-pin PQFP
144-pin TQFP (2)
208-pin PQFP
256-pin FineLine BGA®
256-pin FineLine BGA
484-pin FineLine BGA
256-pin FineLine BGA
484-pin FineLine BGA
Number of Ã8
Groups
3
7 (3)
3
7 (3)
8 (3)
8
16 (4)
8
16 (4)
Number of Ã9 Number of Ã16 Number of Ã18
Groups (5), (6) Groups Groups (5), (6)
3
0
0
4
3
3
3
0
0
4
3
3
4
4
4
4
4
4
8
8
8
4
4
4
8
8
8
2â46
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007
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