EP2C8T144I8N Datasheet, PDF (122/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Timing Specifications
Table 5–15. Cyclone II Performance (Part 4 of 4)
Resources Used
Performance (MHz)
Applications
Larger 8-bit, 1024 pt, Quad Output,
Designs 4 Parallel FFT Engines, Buffered
Burst, 3 Mults/5 Adders FFT
function
8-bit, 1024 pt, Quad Output,
4 Parallel FFT Engines, Buffered
Burst, 4 Mults/2 Adders FFT
function
LEs
M4K
Memory
Blocks
DSP
Blocks
–6
Speed
Grade
8053 60
36 200.0
–7
Speed
Grade
(6)
–7
Speed
Grade
(7)
–8
Speed
Grade
195.0 149.23 163.02
7453 60
48 200.0 195.0 151.28 163.02
Notes to Table 5–15 :
(1) This application uses registered inputs and outputs.
(2) This application uses registered multiplier input and output stages within the DSP block.
(3) This application uses the same clock source for both A and B ports.
(4) This application uses independent clock sources for A and B ports.
(5) This application uses PLL clock outputs that are globally routed to connect and drive M4K clock ports. Use of
non-PLL clock sources or local routing to drive M4K clock ports may result in lower performance numbers than
shown here. Refer to the Quartus II timing report for actual performance numbers.
(6) These numbers are for commercial devices.
(7) These numbers are for automotive devices.
Internal Timing
Refer to Tables 5–16 through 5–19 for the internal timing parameters.
Table 5–16. LE_FF Internal Timing Microparameters (Part 1 of 2)
Parameter
TSU
TH
TCO
TCLR
–6 Speed Grade (1)
Min
Max
–36
—
—
—
266
—
—
—
141
250
—
—
191
—
—
—
–7 Speed Grade (2)
Min
Max
–40
—
–38
—
306
—
286
—
135
277
141
—
244
—
217
—
–8 Speed Grade (3)
Unit
Min
Max
–40
—
ps
–40
—
ps
306
—
ps
306
—
ps
135
304
ps
141
—
ps
244
—
ps
244
—
ps
5–18
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2008