EP2C8T144I8N Datasheet, PDF (241/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Cyclone II Memory Blocks
Input/Output Clock Mode
Cyclone II memory blocks can implement the input/output clock mode
for true and simple dual-port memory. On each of the two ports, A and B,
one clock controls all registers for the data, write enable, and address
inputs into the memory block. The other clock controls the blocks’ data
output registers. Each memory block port also supports independent
clock enables for input and output registers. Asynchronous clear signals
for the registers are not supported.
Figures 8–14 through 8–16 show the memory block in input/output clock
mode for true dual-port, simple dual-port, and single-port modes,
respectively.
Altera Corporation
February 2008
8–19
Cyclone II Device Handbook, Volume 1