EP2C8T144I8N Datasheet, PDF (385/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Configuring Cyclone II Devices
Table 13–7 defines the timing parameters for Cyclone II devices for PS
configuration.
Table 13–7. PS Timing Parameters for Cyclone II Devices
Symbol
t_{P O R}
t_{C F 2 C D}
t_{C F 2 S T 0}
t_{C F G}
t_{S TAT U S}
t_{C F 2 S T 1}
t_{C F 2 C K}
t_{S T 2 C K}
t_{D S U}
t_{D H}
t_{C H}
t_{C L}
t_{C L K}
f_{M A X}
t_{C D 2 U M}
t_{C D 2 C U}
t_{C D 2 U M C}
Parameter
Minimum
Maximum
POR delay (1)
100
nCONFIG low to CONF_DONE low
nCONFIG low to nSTATUS low
nCONFIG low pulse width
2
nSTATUS low pulse width
10
nCONFIG high to nSTATUS high
nCONFIG high to first rising edge on DCLK
40
nSTATUS high to first rising edge on DCLK
1
Data setup time before rising edge on DCLK
7
Data hold time after rising edge on DCLK
0
DCLK high time
4
DCLK low time
4
DCLK period
10
DCLK frequency
CONF_DONE high to user mode (3)
18
800
800
40 (2)
40 (2)
100
40
CONF_DONE high to CLKUSR enabled
4 × maximum DCLK
period
CONF_DONE high to user mode with CLKUSR t_{C D 2 C U} + (299 × CLKUSR
option on
period)
Units
ms
ns
ns
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
MHz
µs
Notes to Table 13–7:
(1) The POR delay minimum of 100 ms only applies for non “A” devices.
(2) This value is applicable if users do not delay configuration by extending the nCONFIG or nSTATUS low pulse
width.
(3) The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
the device.
f
Device configuration options and how to create configuration files are
discussed further in the Software Settings section in Volume 2 of the
Configuration Handbook.
PS Configuration Using a Microprocessor
In the PS configuration scheme, a microprocessor can control the transfer
of configuration data from a storage device, such as flash memory, to the
target Cyclone II device.
Altera Corporation
February 2007
13–31
Cyclone II Device Handbook, Volume 1