EP2C8T144I8N Datasheet, PDF (293/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Selectable I/O Standards in Cyclone II Devices
Figure 10–6. 1.8-V SSTL Class II Termination
V_TT = 0.9 V
V_TT = 0.9 V
Output Buffer
50 Ω
50 Ω
25 Ω
Z = 50 Ω
V_REF = 0.9 V
Input Buffer
1.8-V HSTL Class I and II
The HSTL standard is a technology independent I/O standard developed
by JEDEC to provide voltage scalability. It is used for applications
designed to operate in the 0.0- to 1.8-V HSTL logic switching range such
as quad data rate (QDR) memory clock interfaces.
Although JEDEC specifies a maximum V_CCIO value of 1.6 V, there are
various memory chip vendors with HSTL standards that require a V_CCIO
of 1.8 V. Cyclone II devices support interfaces with V_CCIO of 1.8 V for
HSTL. Figures 10–7 and 10–8 show the nominal V_REF and V_TT required to
track the higher value of V_CCIO. The value of V_REF is selected to provide
optimum noise margin in the system. Cyclone II devices support both
input and output levels of operation.
Figure 10–7. 1.8-V HSTL Class I Termination
Output Buffer
V_TT = 0.9 V
Z = 50 Ω
50 Ω
V_REF = 0.9 V
Input Buffer
Figure 10–8. 1.8-V HSTL Class II Termination
V_TT = 0.9 V
V_TT = 0.9 V
Output Buffer
50 Ω
50 Ω
Z = 50 Ω
V_REF = 0.9 V
Input Buffer
Altera Corporation
February 2008
10–11
Cyclone II Device Handbook, Volume 1