EP2C8T144I8N Datasheet, PDF (325/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

High-Speed Differential Interfaces in Cyclone II Devices
Figure 11–2. I/O Banks in EP2C15, EP2C20, EP2C35, EP2C50 & EP2C70 Devices
I/O Banks 3 & 4 Also Support
the SSTL-18 Class II,
HSTL-18 Class II, & HSTL-15
Class II I/O Standards
I/O Bank 3
I/O Bank 4
I/O Bank 2
I/O Banks 1 & 2 Also
Support the 3.3-V PCI
& PCI-X I/O Standards
I/O Bank 1
Individual
Power Bus
All I/O Banks Support
■ 3.3-V LVTTL/LVCMOS
■ 2.5-V LVTTL/LVCMOS
■ 1.8-V LVTTL/LVCMOS
■ 1.5-V LVCMOS
■ LVDS
■ RSDS
■ mini-LVDS
■ LVPECL (1)
■ SSTL-2 Class I and II
■ SSTL-18 Class I
■ HSTL-18 Class I
■ HSTL-15 Class I
■ Differential SSTL-2 (2)
■ Differential SSTL-18 (2)
■ Differential HSTL-18 (3)
■ Differential HSTL-15 (3)
I/O Bank 5
I/O Banks 5 & 6 Also
Support the 3.3-V PCI
& PCI-X I/O Standards
I/O Bank 6
Regular I/O Block
Bank 8
Regular I/O Block
Bank 7
I/O Banks 7 & 8 Also Support
the SSTL-18 Class II,
HSTL-18 Class II, & HSTL-15
Class II I/O Standards
Notes to Figure 11–2:
(1) The LVPECL I/O standard is only supported on clock input pins. This I/O standard is not supported on output
pins.
(2) The differential SSTL-18 and SSTL-2 I/O standards are only supported on clock input pins and PLL output clock
pins.
(3) The differential 1.8-V and 1.5-V HSTL I/O standards are only supported on clock input pins and PLL output clock
pins.
Cyclone II
High-Speed I/O
Interface
Cyclone II devices provide a multi-protocol interface that allows
communication between a variety of I/O standards, including LVDS,
LVPECL, RSDS, mini-LVDS, differential HSTL, and differential SSTL.
This feature makes the Cyclone II device family ideal for applications that
require multiple I/O standards, such as protocol translation.
Altera Corporation
February 2007
11–3
Cyclone II Device Handbook, Volume 1