EP2C8T144I8N Datasheet, PDF (412/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

JTAG Configuration
Figure 13–23. JTAG Configuration of a Single Device Using a Microprocessor
Memory
Cyclone II FPGA
nCE (3)
ADDR
DATA
(4)
nCEO MSEL1
(2)
(2)
nCONFIG ^MSEL0
(2)
VCC (1)
(2)
DATA0
(2)
DCLK
VCC (1) _{10 kΩ}
TDI
10 kΩ
Microprocessor
TCK
TDO
TMS _nSTATUS
CONF_DONE
Notes to Figure 13–23:
(1) The pull-up resistor should be connected to a supply that provides an acceptable
input signal for all devices in the chain.
(2) Connect the nCONFIG and MSEL[1..0] pins to support a non-JTAG
configuration scheme. If only JTAG configuration is used, connect the nCONFIG
pin to V_CC, and the MSEL[1..0] pins to ground. In addition, pull DCLK and
DATA0 to either high or low, whichever is convenient on your board.
(3) nCE must be connected to GND or driven low for successful JTAG configuration.
(4) If using an EPCS4 or EPCS1 device, set MSEL[1..0] to 00. See Table 13–4 for more
details.
JTAG Configuration of Multiple Devices
When programming a JTAG device chain, one JTAG-compatible header
is connected to several devices. The number of devices in the JTAG chain
is limited only by the drive capability of the download cable. When four
or more devices are connected in a JTAG chain, Altera recommends
buffering the TCK, TDI, and TMS pins with an on-board buffer.
JTAG-chain device programming is ideal when the system contains
multiple devices, or when testing your system using JTAG BST circuitry.
Figure 13–24 shows multiple device JTAG configuration.
13–58
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007