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EP2C8T144I8N Datasheet, PDF (258/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1 | |||
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External Memory Interface Standards
Figure 9â1. Example of a 90° Shift on the DQS Signal Notes (1), (2)
DQS pin to
register delay
DQS at
FPGA pin
Preamble
Postamble
DQ at
FPGA pin
DQS at
IOE registers
90Ë degree (3)
DQ at
IOE registers
DQ pin to
register delay
Notes to Figure 9â1:
(1) RLDRAM II and QDRII SRAM memory interfaces do not have preamble and postamble specifications.
(2) DDR2 SDRAM does not support a burst length of two.
(3) The phase shift required for your system should be based on your timing analysis and may not be 90°.
During write operations to a DDR or DDR2 SDRAM device, the FPGA
must send the data strobe to the memory device center-aligned relative to
the data. Cyclone II devices use a PLL to center-align the data strobe by
generating a 0° phase-shifted system clock for the write data strobes and
a â90° phase-shifted write clock for the write data pins for the DDR and
DDR2 SDRAM. Figure 9â2 shows an example of the relationship between
the data and data strobe during a burst-of-two write.
Figure 9â2. DQ & DQS Relationship During a DDR & DDR2 SDRAM Write
DQS at
FPGA Pin
DQ at
FPGA Pin
9â4
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007
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