EP2C8T144I8N Datasheet, PDF (71/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Cyclone II Architecture
In Cyclone II devices, all the I/O banks support SDR and DDR SDRAM
memory up to 167 MHz/333 Mbps. All I/O banks support DQS signals
with the DQ bus modes of ×8/×9, or ×16/×18. Table 2–14 shows the
external memory interfaces supported in Cyclone II devices.
Table 2–14. External Memory Support in Cyclone II Devices Note (1)
Memory Standard
I/O Standard
SDR SDRAM
DDR SDRAM
DDR2 SDRAM
QDRII SRAM (4)
LVTTL (2)
SSTL-2 class I (2)
SSTL-2 class II (2)
SSTL-18 class I (2)
SSTL-18 class II (3)
1.8-V HSTL class I
(2)
1.8-V HSTL class II
(3)
Maximum Bus
Width
72
72
72
72
72
36
36
Maximum Clock
Rate Supported
(MHz)
167
167
133
167
125
167
100
Maximum Data
Rate Supported
(Mbps)
167
333 (1)
267 (1)
333 (1)
250 (1)
668 (1)
400 (1)
Notes to Table 2–14:
(1) The data rate is for designs using the Clock Delay Control circuitry.
(2) The I/O standards are supported on all the I/O banks of the Cyclone II device.
(3) The I/O standards are supported only on the I/O banks on the top and bottom of the Cyclone II device.
(4) For maximum performance, Altera recommends using the 1.8-V HSTL I/O standard because of higher I/O drive
strength. QDRII SRAM devices also support the 1.5-V HSTL I/O standard.
Cyclone II devices use data (DQ), data strobe (DQS), and clock pins to
interface with external memory. Figure 2–26 shows the DQ and DQS pins
in the ×8/×9 mode.
Altera Corporation
February 2007
2–45
Cyclone II Device Handbook, Volume 1