EP2C8T144I8N Datasheet, PDF (198/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Hardware Features
Figure 7–7. Phase Relationship between Cyclone II PLL Clocks in
Source-Synchronous Compensation Mode
Data pin
inclk
Hardware
Features
Data at register
Clock at register
1 Set the input pin to the register delay chain within the IOE to
zero in the Quartus II software for all data pins clocked by a
source-synchronous mode PLL.
Cyclone II device PLLs support a number of features for general-purpose
clock management. This section discusses clock multiplication and
division implementation, phase-shifting implementation and PLL lock
circuits.
Clock Multiplication & Division
Cyclone II device PLLs provide clock synthesis for PLL output ports
using m/(n × post-scale) scaling factors. Every PLL has one pre-scale
divider, n, with a range of 1 to 4 and one multiply counter, m, with a range
of 1 to 32. The input clock, f_IN, is divided by a pre-scale counter, n, to
produce the input reference clock, f_REF, to the PFD. This input reference
clock, f_REF, is then multiplied by the m feedback factor. The control loop
drives the VCO frequency to match f_IN × (m/n). The equations for these
frequencies are:
f_REF =
f_IN
n
m
f_VCO = f_REF × m = f_{IN n}
7–14
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007