EP2C8T144I8N Datasheet, PDF (276/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

DDR Memory Interface Pins
Figure 9–15. DDR Output Waveforms
outclk
datain_h
D0
D2
D4
D6
D8
datain_l
D1
D3
D5
D7
D9
data1
D0
D2
D4
D6
D8
data0
D1
D3
D5
D7
D9
DQ
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
Bidirectional DDR Registers
Figure 9–16 shows a bidirectional DDR interface constructed using the
DDR input and DDR output examples described in the previous two
sections. As with the DDR input and DDR output examples, the
bidirectional DDR pin can be any available user I/O pin. The registers
that implement DDR bidirectional logic are LEs in the LAB adjacent to
that pin. The tri-state buffer controls when the device drives data onto the
bidirectional DDR pin.
9–22
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007