EP2C8T144I8N Datasheet, PDF (193/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

PLLs in Cyclone II Devices
Table 7–5. PLL Output signals
Port
c[2..0]
Locked
Description
Source
PLL clock outputs driving the internal global clock PLL post-scale
network or external clock output pin
counter
(PLL<#>_OUT)
Gives the status of the PLL lock. When the PLL is
locked, this port drives V_{C C}. When the PLL is out
of lock, this port drives GND. The locked port may
pulse high and low during the PLL lock process.
PLL lock detect
circuit
Destination
Global clock
network or
external I/O pin
Logic array or
output pin
Table 7–6 shows a list of I/O standards supported in Cyclone II device
PLLs.
Table 7–6. I/O Standards Supported for Cyclone II PLLs (Part 1 of 2)
I/O Standard
LVTTL (3.3, 2.5, and 1.8 V)
LVCMOS (3.3, 2.5, 1.8, and
1.5 V)
3.3-V PCI
3.3-V PCI-X (1)
LVPECL
LVDS
1.5 and 1.8 V differential
HSTL class I and class II
1.8 and 2.5 V differential
SSTL class I and class II
1.5-V HSTL class I
1.5-V HSTL class II (3)
1.8-V HSTL class I
1.8-V HSTL class II (3)
SSTL-18 class I
SSTL-18 class II (3)
SSTL-25 class I
Input
inclk
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Output
lock
pll_out
v
v
v
v
v
v
v
v
v
v
v (2)
v (2)
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Altera Corporation
February 2007
7–9
Cyclone II Device Handbook, Volume 1