EP2C8T144I8N Datasheet, PDF (185/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

7. PLLs in Cyclone II Devices
CII51007-3.1
Introduction
Cyclone^® II devices have up to four phase-locked loops (PLLs) that
provide robust clock management and synthesis for device clock
management, external system clock management, and I/O interfaces.
Cyclone II PLLs are versatile and can be used as a zero delay buffer, a
jitter attenuator, a low skew fan out buffer, or a frequency synthesizer.
Each Cyclone II device has up to four PLLs, supporting advanced
capabilities such as clock switchover and programmable switchover.
These PLLs offer clock multiplication and division, phase shifting, and
programmable duty cycle and can be used to minimize clock delay and
clock skew, and to reduce or adjust clock-to-out (t_CO) and set-up (t_SU)
times.
Cyclone II devices also support a power-down mode where unused clock
networks can be turned off. The Altera^® Quartus^® II software enables the
PLLs and their features without requiring any external devices.
1 Cyclone II PLLs have been characterized to operate in the
commercial junction temperature range (0° to 85° C), the
industrial junction temperature range (-40° to 100° C) and the
extended temperature range (-40° to 125° C).
Table 7–1 shows the PLLs available in each Cyclone II device.
Table 7–1. Cyclone II Device PLL Availability
Device
EP2C5
EP2C8
EP2C15
EP2C20
EP2C35
EP2C50
EP2C70
PLL1
v
v
v
v
v
v
v
PLL2
v
v
v
v
v
v
v
PLL3
v
v
v
v
v
PLL4
v
v
v
v
v
Altera Corporation
7–1
February 2007