EP2C8T144I8N Datasheet, PDF (265/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

External Memory Interfaces
In ×8 and ×16 modes, one DQS pin drives up to 8 or 16 DQ pins,
respectively, within the group. In the ×9 and ×18 modes, a pair of DQS
pins (CQ and CQ#) drives up to 9 or 18 DQ pins within the group to
support one or two parity bits and the corresponding data bits. If the
parity bits or any data bits are not used, the extra DQ pins can be used as
regular user I/O pins. The ×9 and ×18 modes are used to support the
QDRII memory interface. Table 9–2 shows the number of DQS/DQ
groups supported in each Cyclone II density/package combination.
Table 9–2. Cyclone II DQS & DQ Bus Mode Support Note (1)
Device
EP2C5
EP2C8
EP2C15
EP2C20
EP2C35
EP2C50
EP2C70
Package
144-pin TQFP (2)
208-pin PQFP
256-pin FineLine BGA
144-pin TQFP (2)
208-pin PQFP
256-pin FineLine BGA^®
256-pin FineLine BGA
484-pin FineLine BGA
240-pin PQFP
256-pin FineLine BGA
484-pin FineLine BGA
484-pin FineLine BGA
672-pin FineLine BGA
484-pin FineLine BGA
672-pin FineLine BGA
672-pin FineLine BGA
896-pin FineLine BGA
Number of ×8
Groups
3
7 (3)
8 (3)
3
7 (3)
8 (3)
8
16 (4)
8
8
16 (4)
16 (4)
20 (4)
16 (4)
20 (4)
20 (4)
20 (4)
Number of ×9 Number of ×16 Number of ×18
Groups (5), (6) Groups Groups (5), (6)
3
0
0
4
3
3
4 (7)
4
4 (7)
3
0
0
4 (7)
3
3
4 (7)
4
4 (7)
4
4
4
8 (8)
8
8 (8)
4
4
4
4
4
4
8 (8)
8
8 (8)
8 (8)
8
8 (8)
8 (8)
8
8 (8)
8 (8)
8
8 (8)
8 (8)
8
8 (8)
8 (8)
8
8 (8)
8 (8)
8
8 (8)
Notes to Table 9–2:
(1) Numbers are preliminary.
(2) EP2C5 and EP2C8 devices in the 144-pin TQFP package do not have any DQ pin groups in I/O bank 1.
(3) Because of available clock resources, only a total of 6 DQ/DQS groups can be implemented.
(4) Because of available clock resources, only a total of 14 DQ/DQS groups can be implemented.
(5) The ×9 DQS/DQ groups are also used as ×8 DQS/DQ groups. The ×18 DQS/DQ groups are also used as ×16
DQS/DQ groups.
(6) For QDRII implementation, if you connect the D ports (write data) to the Cyclone II DQ pins, the total available ×9
DQS /DQ and ×18 DQS/DQ groups are half of that shown in Table 9–2.
(7) Because of available clock resources, only a total of 3 DQ/DQS groups can be implemented.
(8) Because of available clock resources, only a total of 7 DQ/DQS groups can be implemented.
Altera Corporation
February 2007
9–11
Cyclone II Device Handbook, Volume 1