EP2C8T144I8N Datasheet, PDF (250/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Read-During- Write Operation at the Same Address
Read-During-
Write Operation
at the Same
Address
The “Same-Port Read-During-Write Mode” and “Mixed-Port
Read-During-Write Mode” sections describe the functionality of the
various RAM configurations when reading from an address during a
write operation at that same address. There are two read-during-write
data flows: same-port and mixed-port. Figure 8–21 shows the difference
between these flows.
Figure 8–21. Cyclone II Read-During-Write Data Flow
Port A
data in
Port B
data in
Port A
data out
Port B
data out
Mixed-port
data flow
Same-port
data flow
Same-Port Read-During-Write Mode
For read-during-write operation of a single-port RAM or the same port of
a true dual-port RAM, the new data is available on the rising edge of the
same clock cycle on which it was written. Figure 8–22 shows a sample
functional waveform. When using byte enables in true dual-port RAM
mode, the outputs for the masked bytes on the same port are unknown
(see Figure 8–2 on page 8–6). The non-masked bytes are read out as
shown in Figure 8–22.
8–28
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2008