EP2C8T144I8N Datasheet, PDF (272/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

DDR Memory Interface Pins
Figure 9–10. Cyclone II DQS Postamble Circuitry Control Timing Waveform
DQS
DQS'
Reset
EnableN
DDR Input Registers
In Cyclone II devices, the DDR input registers are implemented with five
internal LE registers located in the logic array block (LAB) adjacent to the
DDR input pin (see Figure 9–11). The DDR data is fed to the first two
registers, input register A_I and input register B_I. Input register B_I
captures the DDR data present during the rising edge of the clock. Input
register A_I captures the DDR data present during the falling edge of the
clock. Register C_I aligns the data before it is transferred to the
resynchronization registers.
Figure 9–11. DDR Input Implementation
dataout_h
LE
Register
DDR Input Configuration in Cyclone II
LE
Register
dataout_l
sync_reg_h
LE
Register
LE
Register
Input Register A I
neg_reg_out
LE
Register
sync_reg_l
Register C_I
Input Register BI
Inverted &
Delayed DQS
DQ
Clock Delay
Control Circuitry
resynch_clk
t
DQS
9–18
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007