EP2C8T144I8N Datasheet, PDF (418/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Device Configuration Pins
Device
Configuration
Pins
Reconfiguration
After all the configuration data is written into the serial configuration
device successfully, the Cyclone II device does not reconfigure by itself.
The intelligent host issues the PULSE_NCONFIG JTAG instruction to
initialize the reconfiguration process. During reconfiguration, the master
Cyclone II device is reset and the serial flash loader design no longer
exists in the Cyclone II device and the serial configuration device
configures all the devices in the chain with your user design.
This section describes the connections and functionality of all the
configuration related pins on the Cyclone II device. Table 13–11 describes
the dedicated configuration pins, which are required to be connected
properly on your board for successful configuration. Some of these pins
may not be required for your configuration schemes.
Table 13–11. Dedicated Configuration Pins on the Cyclone II Device (Part 1 of 5)
Pin Name
User Configuration
Mode Scheme
Pin Type
MSEL[1..0] N/A All
Input
Description
This pin is a two-bit configuration input that sets the
Cyclone II device configuration scheme. See
Table 13–1 for the appropriate settings.
You must connect these pins to V_{C CI O} or ground.
nCONFIG
N/A All
Input
The MSEL[1..0] pins have 9-kΩ internal
pull-down resistors that are always active.
This pin is a configuration control input. If this pin is
pulled low during user mode, the FPGA loses its
configuration data, enters a reset state, and tri-states
all I/O pins. Transitioning this pin high initiates a
reconfiguration.
If your configuration scheme uses an enhanced
configuration device or EPC2 device, you can
connect the nCONFIG pin directly to V_CC or to the
configuration device's nINIT_CONF pin.
The input buffer on this pin supports hysteresis using
Schmitt trigger circuitry.
13–64
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007